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Download MicroBlaze ™ Hardware Reference Guide
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R OPB Simple Interrupt Controller Specification Unless stated otherwise any register bits that are not mapped to inputs return zero when read and do nothing when written. Table 13: IntC Registers and Base Address Offsets Register Name Abbreviation OPB Offset Interrupt Status Register ISR 0 (00h) Interrupt Pending Register IPR 4 (04h) Interrupt Enable Register IER 8 (08h) Interrupt Acknowledge Register IAR 12 (0Ch) Set Interrupt Enable Bits SIE 16 (10h) Clear Interrupt Enable Bits CIE 20 (14h) Interrupt Vector Register IVR 24 (18h) Master Enable Register MER 28 (1Ch) March 2002 MicroBlaze Hardware Reference Guide www.xilinx.com 1-800-255-7778 99
