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HARDWARE REGISTERS
(*3) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the
assertion of EXIINT
(*5) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the
assertion of EXICPR[EXTINT]
(*4) This interrupt indicates than an external EXI device has been removed from channel 1. To check
whether the device has been inserted or removed, check the EXICPR[EXT] bit. When this bit is set, the
channel’s expansion EXI interface outputs go to high.
0xCC006804
0xCC006818
0xCC00682c
4
4
4
31
....
23
dddd
24
..dd
r/w
r/w
r/w
EXI0MAR - EXI Channel 0 DMA Start Address
EXI1MAR - EXI Channel 1 DMA Start Address
EXI2MAR - EXI Channel 2 DMA Start Address
16
dddd
15
dddd
8
dddd
7
ddd.
0
....
Physical Startaddress for DMA transfer. Must be aligned to 32 byte boundary .
(*) The memory address is the destination address when EXICR[RW] is set to ‘read‘ and is the source
address when set to ‘write‘.
0xCC006808
0xCC00681c
0xCC006830
4
4
4
31
....
23
dddd
24
..dd
r/w EXI0LENGTH - EXI Channel 0 DMA Transfer Length
EXI Channel 1 DMA Transfer Length
EXI Channel 2 DMA Transfer Length
16
dddd
15
dddd
8
dddd
7
ddd.
0
....
Size of DMA transfer data in bytes. bits 0-4 are always zero (which means the size is 32 byte aligned)
0xCC00680c
0xCC006820
0xCC006834
4
4
4
31
....
23
....
24
....
bit(s)
6-31
4-5
.
l
2-3
t
1
0
m
e
r/w
r/w
r/w
EXI0CR - EXI Channel 0 Control Register
EXI1CR - EXI Channel 1 Control Register
EXI2CR - EXI Channel 2 Control Register
16
....
15
....
8
....
7
..ll
0
ttme
Description
unused
TLEN - (data length-1) for immediate mode
00 1 byte
01 2 bytes
10 3 bytes
11 4 bytes
RW - transfer type
00 read
01 write
10 read and write, invalid for DMA
11 undefined
DMA - transfer mode (0 - immediate, 1 - DMA)
TSTART - set, to start transfer. will be cleared after transfer completed.