Download PowerPC MMU Simulation

Appendix C Register summary
This appendix summarises all registers implemented in the simulator developed in this
thesis.
PPC-405GP Programming model-registers
The following part lists the registers implemented in this thesis work. The Figure C.1 below
shows the complete register-model of PPC-405GP. The registers marked with dark grey
colour are not implemented in this study. Most of the registers still not implemented are
support debug and timer features, and there are also registers for handling the real addressing
mode. Registers implemented in the UISA simulator, developed by Seffel, are marked with
light grey colour and the unmarked registers are implemented in this study. As one can see the
most of the registers implemented in this extended UISA simulator are supervisor state
registers, and this is because the MM is controlled at the supervisor-level.
53