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state when the 604e must recover from a mispredicted branch, or any other exception or
interrupt.
The rate of instruction completion is unaffected by the 604e’s ability to write the instruction
results from the rename registers to the architecturally defined registers when the
instruction is retired. The 604e can perform two write-back operations from each of the
rename registers to the register files (CR, GPRs, and FPRs) each clock cycle.
Due to the 604e’s out-of-order execution capability, the in-order completion of instructions
by the completion unit provides a precise exception mechanism. All program-related
exceptions are signaled when the instruction causing the exception has reached the last
position in the completion buffer. All prior instructions are allowed to complete and write
back before the exception is taken.
6.4.6.1 Rename Register Operation
To avoid contention for a given register file location in the course of out-of-order execution,
the 604e provides rename registers for the storage of instruction results prior to their
commitment (in program order) to the architecturally defined register by the completion
unit. Register renaming minimizes architectural resource dependencies, namely the output
and antidependencies, that would otherwise limit opportunities for out-of-order execution.
Twelve rename registers are provided for the GPRs, eight for the FPRs, and eight for the
condition register.
A GPR rename buffer entry is allocated when an instruction that modifies a GPR is
dispatched. This entry is marked as allocated but not valid. When the instruction executes,
it writes its result to the entry and sets the valid bit. When the instruction completes, its
result is copied from the rename buffer entry to the GPR and the entry is freed for
reallocation. For load with update instructions that modify two GPRs, one for load data and
another for address, two rename buffer entries are allocated.
The rename register for the GPRs is shown in Figure 6-12.
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PowerPC 604e RISC Microprocessor User's Manual