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5.1.5 General functionality of the IP core
The LCD IP core is able to receive read and write transfers from the LEON3 processor
through the APB bus. The read and write transfers have to be addressed to the address
space of the LCD IP core in order for the transfers to have an effect. A write transfer is
passed on to the LCD device and interpreted as an instruction, while a read transfer
simply reads the contents of PRDATA. The write transfer to the LCD device is passed
on using a finite-state machine which fulfills a number of critical timing requirements.
This state machine is explained later in this section.
APB write transfer
A write transfer on the APB bus to the IP core is identified by checking the APB slave
inputs PSEL, PENABLE and PWRITE described in section 2.2.2. If all of these inputs
are asserted it means that the IP core is selected, the APB bus is enabled for a bus
transfer and the requested transfer is a write. If PADDR[3:2] = “11” during the write
transfer, this indicates that the processor wants to write to the configuration register. In
this case, PWDATA[3:0] corresponds to tas and PWDATA[10:4] corresponds to epw.
For a write transfer to any other address of the LCD device address space, the received
transfer is interpreted as an instruction code given to the LCD device according to Table
8 in section 2.5.3. When interpreting this instruction, PWDATA[7:0] is translated to
DB7-DB0, PWDATA[8] is the R/W signal and PWDATA[9] is the RS signal.
As was explained in section 5.1.2 there is a potential problem if the instruction written
to the LCD device is a read instruction. This problem was solved by introducing an
internal busy flag in the LCD IP core that can be polled by the processor. The purpose
of this flag is to prevent the processor from reading the contents of PRDATA before it
has been updated with valid data for the current read operation. By doing so the busy
flag acts as a valid bit for the PRDATA register content. The correct read data to return
is sampled to PRDATA on the falling edge of the enable signal, as can be seen in
Figure 13 in section 2.5.5.
APB read transfer
Whenever a read transfer on the APB bus is done to the IP core, the content of
PRDATA is read. As can be seen in Figure 18, this register consists of the read data
retrieved from the last read instruction performed, the internal busy flag of the IP core,
tas and epw. In order to trust that the read data is valid, PRDATA[8], which is the valid
bit for the read data, has to be checked after performing a read instruction. When this bit
is low it is an indication that the read data is valid.
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