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Download GRLIB IP Core User`s Manual
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AEROFLEX GAISLER 554 GRIP 56.2.6 Multiply and accumulate instructions To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made up by the 8 lsb bits from the %y register and the %asr18 register. The least significant 32 bits are also written to the destination register. SMAC works similarly but performs signed multiply and accumulate. The MAC instructions execute in one clock but have two clocks latency, meaning that one pipeline stall cycle will be inserted if the following instruction uses the destination register of the MAC as a source operand. Assembler syntax: umacrs1, reg_imm, rd smacrs1, reg_imm, rd Operation: prod[31:0] = rs1[15:0] * reg_imm[15:0] result[39:0] = (Y[7:0] & %asr18[31:0]) + prod[31:0] (Y[7:0] & %asr18[31:0]) = result[39:0] rd = result[31:0] %asr18 can be read and written using the RDASR and WRASR instructions. 56.2.7 Branch prediction Static branch prediction can be optionally be enabled, and reduces the penalty for branches preceeded by an instruction that modifies the integer condition codes. The predictor uses a branch-always strategy, and starts fetching instruction from the branch address. On a prediction hit, 1 or 2 clock cycles are saved. No extra penalty incures for mis-prediction. Branch prediction improves the performance with 10 - 20% on most control-type applications. 56.2.8 Hardware breakpoints The integer unit can be configured to include up to four hardware breakpoints. Each breakpoint consists of a pair of application-specific registers (%asr24/25, %asr26/27, %asr28/29 and %asr30/31) registers; one with the break address and one with a mask: 31 %asr24, %asr26 %asr28, %asr30 2 WADDR[31:2] 31 %asr25, %asr27 %asr29, %asr31 0 IF 2 WMASK[31:2] 1 0 DL DS Figure 178. Watch-point registers Any binary aligned address range can be watched - the range is defined by the WADDR field, masked by the WMASK field (WMASK[x] = 1 enables comparison). On a breakpoint hit, trap 0x0B is generated. By setting the IF, DL and DS bits, a hit can be generated on instruction fetch, data load or data store. Clearing these three bits will effectively disable the breakpoint function.
