Download MCX314As/AL User`s Manual

MCX314As/AL – M61
NOVA electronics Inc.
Additionally, bits D7 (PLS-L) and D8 (DIR-L) of register WR2 can be used for pulse outputting, direction and logical level
setting.
[Note] Please refer to Chapter 14.2 and 14.3 for the pulse signal (nPLS) and direction signal (nDIR) in 1- pulse 1-direction pulse
outputting.
2.9.3 Pulse Input Type Selection
For real position counter, quadrature pulses type and Up / Down pulse type can be selected for pulse input.
Quadrature pulses input mode
A quadrature pulses input mode can be set by setting the D9 (PINMD) bit of the WR2 register to 0. In this mode, when A phase
is advancing with positive logical pulses, the count is incremented and when the B-phase is advancing, the count is decremented.
The count is incremented and decremented at the rising edge and falling edge of both signals. When the real position counter
up/down reverse bit (WR6/D1) is set to 1 in extension mode setting, the up/down operation of the real counter is reversed. (See
Section 6.16.)
In quadrature pulses input mode, the input pulses can be divided into 1/2 or 1/4.
nECA/PPIN
nECB/PMIN
Extention Mode Setting WR6/D1(EPINV)= 0
at reset
Count up at the both signals
Count down at the both signals
Extention Mode Setting WR6/D1(EPINV)= 1
Count down at the both signals
Count up at the both signals
Up/down pulse input mode
By setting the D9 (PINMD) bit of the WR2 register to 1, a counter up/down pulse input mode can be set. nECA/PPIN is count up
input and nECB/PMIN is count down input. The counter counts at the rising edge of the positive pulse.
nECA/PPIN
nECB/PMIN
Count up
Count down
Use the D9 (PINMD) bit of the WR2 register for selecting a pulse input mode and the D11 and D10 (PIND1,0) bits to set the
division ratio of encoder 2-phase pulse input.
[Note] Time specification is applied to the pulse width and pulse cycle of input pulses. See Section 13.2.5 Input Pulse of Chapter
13.
2.9.4 Hardware Limit Signals
Hardware limit signals, nLMTP and nLMTM, are used for stopping the pulse output if the limit sensors of + and − directions are
triggered.
When the limit signal and also the logical level are active, the command of sudden stop or decelerating stop can be set by bits D3
and D4 (HLMT+, HLMT−), and D2 (LMTMD) of register WR2.
2.9.5 Interface to Servo Motor Drivers
Enable / Disable and logical levels of the input signals for connecting servo motor drivers such as nINPOS (in-position input
signal) and nALARM (alarm input signal) can be set by D15~12 bits of register WR2. nINPOS input signal responds to the
in-position signal of servo motor driver.
When “enable” is set, and when the driving is finished, nINPOS will wait for the “active”. Then, the n-DRV bit of main status
register PRO will return to 0.
nALARM input signal receives the alarm signal from servo motor drivers. When “enable” is set, nALARM signal will be
monitored, and the D4 (alarm) bit of RR2 register is 1 when nALARM is active. The sudden stop will occur in the driving when
this signal is active.
– 61 –