Download MCX314As/AL User`s Manual

MCX314As/AL – M73
NOVA electronics Inc.
D7,5,3,1
INm-E
The bit for setting enable / disable of driving stop input signal INm 0: disable, 1: enable
D6,4,2,0
INm-L
The bit for setting enable logical levels for input signal INm 0: stop on the Low level, 1:stop on the Hi
level
In automatic home search, the logical level of the INm signal that is used is set in these bits. The
Enable/Disable bits (D5, D3, and D1) are set to Disable.
For the following bits, the interrupt is set: 1: enable, 0: disable
D8
PULSE
Interrupt occurs when the pulse is up (↑) (drive pulse is set on the positive logical level)
D9
P ≥ C−
Interrupt occurs when the value of logical / real position counter is larger than or equal to that of COMP−
register
D10
P < C−
Interrupt occurs when the value of logical / real position counter is smaller than that of COMP− register
D11
P < C+
Interrupt occurs when the value of logical / real position counter is smaller than that of COMP+ register
D12
P ≥ C+
Interrupt occurs when the value of logical / real position counter is larger than or equal to that of COMP+
register
D13
C-END
Interrupt occurs at the end of the constant speed drive during an acceleration / deceleration driving
D14
C-STA
Interrupt occurs at the start of the constant speed drive during an acceleration / deceleration driving
D15
D-END
Interrupt occurs when the driving is finished
D15~D0 will be set to 0 while resetting.
4.5 Mode Register2: WR2
Each axis is with mode register WR2. The axis specified by NOP command or the condition before decides which axis’s register
will be written.
WR2 can be used for setting: (1). external limit inputs, (2). driving pulse types, (3). encoder signal types, and (4). the feedback
signals from servo drivers.
D15
WR2
INP -E
D14
D13
D12
H
D11
D10
D9
D8
D7
D6
D5
D4
NP -L ALM -E ALM -L PIND1 PIND0 PINMD DIR -L PLS -L PLSMD CMPSL HLMT-
L
D3
D2
D1
D0
HLMT+ LMTMD SLMT- SLMT+
D0
SLMT+
Enable / disable setting for COMP+ register which is used as the + direction software limit 1: enable, 0:
disable
Once it is enabled during the + direction driving, if the value of logical / real position counter is larger
than that of COMP+, the decelerating stop will be performed. The D0 (SLMT+) bit of register RR2 will
become 1. Under this situation, further written + direction driving commends will not be executed.
Note: When an extension mode position counter variable ring is used, a software over run limit cannot be
used.
D1
SLMT−
Enable / disable setting for COMP− register which is used as the − direction software limit 1: enable, 0:
disable
Once it is enabled during the − direction driving, if the value of logical / real position counter is smaller
than that of COMP+, the decelerating stop will be performed. The D1 (SLMT−) bit of register RR2 will
become 1. Under this situation, further written − direction driving commends will not be executed.
D2
LMTMD
The bit for controlling stop type when the hardware limits (nLMTP and nLMTM input signals) are active
0: sudden stop, 1: decelerating stop
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