Download LEON/GRLIB Configuration and Development Guide

5
2
System Design Guidelines
2.1
Introduction
The design and partitioning of a system strongly depends on the intended use for the system. The
sections below make general recommendations based on the components available in GRLIB.
2.2
Minimal System
A minimal LEON/GRLIB system consists of the following IP cores:
TABLE 1. Minimal LEON system
Core
Description
CLKGEN
Clock generator
RSTGEN
Reset generator. Generating a glitch free on-chip system reset signal.
AHBCTRL
AHB arbiter/controller.
APBCTRL
AHB/APB bridge/controller. Must be included in order to interface
peripheral cores such as interrupt controller and timer unit.
LEON3/4
LEON3/4 processor
IRQMP
Interrupt controller
GPTIMER
General Purpose Timer Unit
MEMCTRL
Memory controller providing access to (P)ROM and RAM. The
GRLIB IP Library contains several memory controllers. It is also possible to include on-chip ROM and RAM by using the AHBROM and
AHBRAM IP cores.
In addition to the cores described above it is recommended to include a LEON Debug Support
Unit (DSU) and a debug communication link to be able to control the processor and inspect the
system via the GRMON Debug Monitor. GRLIB contains several debug communication link
(DCL) cores. All DCL cores are controlled over an external link to make accesses on an on-chip
AHB bus. Examples of DCL cores are the AHBJTAG, AHBUART and USBDCL cores. See section 5 for more information.
In order for the processor to be able to communicate with the outside world, an 8-bit UART and a
General Purpose I/O port is also typically included in a LEON design.
With the above considerations the recommended minimal LEON/GRLIB system also includes the
following cores:
TABLE 2. Additional recommended cores for minimal LEON system
Core
Description
DSU3/4
LEON Debug Support Unit
AHBJTAG/
AHBUART/
USBDCL/
GRETH
Debug communication link. AHBJTAG provides an external JTAG
link. Other examples include AHBUART (serial UART), USBDCL
(USB), GRETH (Ethernet debug communication link is available as
part of Ethernet MAC core).
APBUART
8-bit UART
GRGPIO
General Purpose I/O Port