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Download 6502 Kit User`s Manual - Build Your Own Microcontroller Projects
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6502 Microprocessor Kit User's Manual 6502 MICROPROCESSOR KIT CONTENTS OVERVIEW...........................................................................................3 FUNCTIONAL BLOCK DIAGARM........................................................3 HARDWARE LAYOUT...........................................................................4 KEYBOARD LAYOUT............................................................................5 HARDWARE FEATURES......................................................................6 MEMORY AND I/O MAPS......................................................................6 GPIO1 LED.............................................................................................7 CONNECTING KIT TO TERMINAL.......................................................8 EXPANSION BUS HEADER..................................................................9 10ms TICK GENERATOR....................................................................10 RS232C PORT......................................................................................11 DATA FRAME for UART COMMUNICATION......................................11 CONNECTING LCD MODULE.............................................................13 LOGIC PROBE POWER SUPPLY........................................................16 WRITE YOUR OWN MONITOR PROGRAM........................................17 HARDWARE SCHEMATIC, BOM.........................................................18 MONITOR PROGRAM LISTINGS.........................................................22 OVERVIEW The 6502 Microprocessor kit is a new design single board computer using the G65SC02 as a CPU. This single board computer is a basic learning tool for programming the 6502 with low level instructions hex code. The board has hex keypad and 7-segment display for entering the instruction hex code and test it directly. Students will learn basic of the computer hardware and software of the 6502 easily. The manual also provides monitor program listings, the method to modify or write your own monitor program. 6502 KIT FUNCTIONAL BLOCK DIAGRAM Notes 1. UART is software control for low speed asynchronous communication. 2. The kit provides 8-bit LCD module interfacing bus. 3. 100Hz Tick generator is for interrupt experiment. 4. Ports for display and keypad interfacing were built with discrete logic IC chips. 5. Memory and Port decoders are made with Programmable Logic Device, PLD. 3 HARDWARE LAYOUT RS232C connector, DB9 male DC jack, +9VDC GPIO1 LED, 8-bit binary display (address is 40H) LCD contrast adj. 20-pin Text LCD header. Selector for 10ms tick or IRQ key Important Notes 1. Plugging or removing the LCD module must be done when the kit is powered off! 2. AC adapter should provide approx. +9VDC, higher voltage will cause the voltage regulator chip becomes hot. 3. The kit has diode protection for wrong polarity of adapter jack. If the center pin is not the positive (+), the diode will be reverse bias, preventing wrong polarity to feed to voltage regulator. 4 KEYBOARD LAYOUT HEX keys Hexadecimal number 0 to F with associated user registers, flag bits and page zero memory $00 to $09 (use with key REG) CPU control keys RESET Reset the CPU, the 6502 will get reset vector from location FFFC and FFFD USER User key for lab test, active low IRQ Make IRQ pin to logic low, used for experimenting with interrupt process Monitor function keys REP Repeat the key that pressed, must be pressed together with REP key. INS N/A. DEL N/A STEP Execute user code only single instruction and return to save CPU registers GO Jump from monitor program to user code - Decrement current display address by one + Increment current display address by one PC Set current display address with user Program Counter REG Display user registers, flags or page zero $00 to $09 with HEX key. DATA Set entry mode of hex keys to Data field ADDR Set entry mode of hex keys to Address field COPY N/A REL Compute relative byte, used with key + for Start, Destination and key GO SEND N/A LOAD Load Intel or MOS hex file at 2400 bit/s using serial port Note, N/A=not available for the current version of monitor program HARDWARE FEATURES The hardware features are as follows; • • • • • • • • • • CPU: 65SC02, CMOS 8-bit Microprocessor @1MHz clock Memory: 32kB RAM, 16kB EPROM Memory and I/O Decoder chip: Programmable Logic Device GAL16V8D Display: 6-digit 7-segment LED Keyboard: 36 keys RS232 port: software controlled UART 2400 bit/s 8n1 Debugging LED: 8-bit GPIO1 LED at location $8000 Tick: 10ms tick produced by 89C2051 Text LCD interface: direct CPU bus interface text LCD Expansion header: 40-pin header 6 MEMORY AND I/O MAPS The first 32kB is RAM space from 0000-7FFFH. Zero page is location 00-FFH. Stack space is 100-1FFH. User space is from 200H to 7FFFH. The 6502 CPU uses memory space from 8000H-BFFFH for I/O port. The monitor ROM is located at C000H-FFFFH Memory mapped I/O 64kB Memory 0000H 32kB RAM 7FFFH 8000H 9000H C000H FFFFH 16kB Monitor ROM 8000H 8001H 8002H 8003H GPIO1 PORT0 PORT1 PORT2 9000H LCD command WR 9001H LCD data WR 9002H LCD command RD 9003H LCD data RD GPIO1 LED The 6502 kit provides a useful 8-bit binary display. It can be used to debug the program or code running demonstration. The I/O address is 8000H. U14 is 8-bit data latch. Logic 1 at the output will make LED lit. The GPIO1 LED can be used to display accumulator register easily. Let us take a look the sample code below. Address 0200 0202 Hex code A9 01 8D 00 80 Label MAIN Instruction LDA #1 STA $8000 comment Load register A with 1 Write A to GPIO1@ 8000H The test code has only two instructions. The first instruction has two bytes machine code, A9 and 01. The second instruction has three bytes, 8D, 00 and 80. Enter the hex code to memory from 0200 to 0203. Then press PC, and execute the instruction with single step by pressing key STEP. The 2nd press STEP key that executes instruction STA $8000 will make the GPIO1 LED showing the content of register A. Try change the load value to register A. Another sample is with JUMP instruction. The JUMP instruction will change the Program Counter to 0200, to repeat program running. Now we use zero page at location 0 to be the byte to be incremented. After incrementing, we load it to register A then write to location of GPIO1 at 8000H. And with JMP LOOP instruction, the program will be repeated. Address 0200 0202 0204 0207 Hex code E6 00 A5 00 8D 00 80 4C 00 02 Label LOOP Instruction INC $0 LDA $0 STA $8000 JMP LOOP comment Increment location 0 Load A with location 0 Write A to GPIO1@ 8000H Jump back to loop Again enter the hex code to memory and test it with single step. Now press key STEP and key REP together. Every time when instruction STA $8000 was executed, did you see the binary number counting? We will learn more the use of GPIO1 with 6502 Programming Lab Book. 8 CONNECTING 6502 KIT TO TERMINAL For LOAD key, we can connect the 6502 kit to a terminal by RS232C cross cable. You may download free terminal program, teraterm from this URL, http://ttssh2.sourceforge.jp/index.html.en RS232C cross cable VT100 Terminal 6502 Kit The example shows connecting laptop with COM1 port to the RS232C port of the 6502 kit. New laptop has no COM port, we may use the USB-RS232 adapter for converting the USB port to RS232 port. To download Intel or MOS hex file that generated from the assembler or c compiler, set serial port speed to 2400 bit/s, 8-data bit, no parity, no flow control, one stop bit. 9 Press key LOAD, then key GO. The kit will wait for the data stream from terminal. On PC, Click file>Send File>LED.HEX. The kit will read the hex file, write to memory, when completed the start message will be displayed. The kit accepts for both Intel or MOS hex files. EXPANSION BUS HEADER JP1, 40-pin header provides CPU bus signals for expansion or I/O interfacing. Students may learn how to make the simple I/O port, interfacing to Analog-to-Digital Converter, interfacing to stepper motor or AC power circuits. 10 USER KEY User key, S19 is one bit active low key switch connected to bit 6 of Port 0. To test the logic of S19, we can use instruction LDA $8001 and check bit 6 of the accumulator with test bit instruction. 10ms TICK GENERATOR SW1 is a selector for interrupt source between key IRQ or 10ms tick produced by 89C2051 microcontroller. Tick generator is software controlled using timer0 interrupt in the 89C2051 chip. The active low tick signal is sent to P3.7. For tick running indicator, P1.7 drives D1 LED. 11 Tick is a 10ms periodic signal for triggering the 6502 IRQ pin. When select SW1 to Tick, the 6502 CPU can be triggered by a maskable interrupt. The 100Hz tick or 10ms tick can be used to produce tasks that executed with multiple of tick. The 6502 kit lab look will show how to use 10ms tick to make a digital timer. 10ms 10ms 10ms RS232C PORT The RS232C port is for serial communication. We can use a cross cable or null MODEM cable to connect between the kit and terminal, or kit #1 to kit #2 for sending or receiving hex file. The connector for both sides are DB9 female. We may build it or buying from computer stores. For new PC or laptop computer with USB port, we may have the RS232C port by using the USB to RS232 converter. 12 DATA FRAME for UART COMMUNICATION Serial data that communicated between kit and terminal is asynchronous format. The 6502 kit has no UART chip, instead it uses software controlled to produce bit rate of 2400 bit/s. The data frame is composed of start bit, 8-data bit and stop bit. For our kit, period = 1/2400 = 417 microseconds. Since bit period is provided by machine cycle delay. Thus to send/receive serial data correctly, all interrupts must be disabled. CONNECTING LCD MODULE JR1 is 20-pin header for connecting the LCD module. The example shows connecting the 16x2 lines text LCD module. R12 is a current limit resistor for back-light. R13 is trimmer POT for contrast adjustment. The LCD module is interfaced to the 6502 bus directly. The command and data registers are located in I/O space having address from 9000H to 9003H. Be advised that plugging or removing the LCD module must be done when the kit is powered off. Text LCD module accepts ASCII codes for displaying the message on screen. Without settings the LCD by software, no characters will be displayed. The first line will be black line by adjusting the R18 for contrast adjustment. 13 Here is the example program that prints text 6502 Kit on the LCD screen. 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 0060 0061 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0200 0200 0200 0203 0203 0203 0203 0203 0204 0207 0209 020B 020C 020D 020D 020D 020D 0210 0213 0214 0214 0214 0217 021A 021B 021B 021B 021E 0220 0223 0224 0224 0226 0229 022B 022E 0231 0233 0235 0238 0239 0239 0239 0239 0239 ; LCD test program for 6502 KIT BUSY .EQU 80H ; below LCD's registers are mapped into memory space command_write data_write command_read data_read .EQU .EQU .EQU .EQU 9000H 9001H 9002H 9003H .cseg .org 200h 4C 5A 02 jmp main ; wait until LCD ready bit set 48 AD 02 90 29 80 D0 F9 68 60 20 03 02 8D 00 90 60 LcdReady ready PHA LDA command_read AND #BUSY BNE ready ; loop if busy flag = 1 PLA RTS LCD_command_write JSR LcdReady STA command_write RTS 20 03 02 8D 01 90 60 LCD_data_write 20 03 02 A9 01 20 0D 02 60 clr_screen JSR LcdReady LDA #1 JSR LCD_command_write RTS A9 20 A9 20 20 A2 A0 20 60 InitLcd LDA #38H JSR LCD_command_write LDA #0CH JSR LCD_command_write JSR clr_screen LDX #0 LDY #0 JSR goto_xy RTS 38 0D 0C 0D 1B 00 00 39 02 02 02 02 JSR LcdReady STA data_write RTS ; goto_xy(x,y) ; entry: A = y position ; B = x position 14 0062 0239 0063 0239 8A goto_xy TXA 0064 023A C9 00 CMP #0 0065 023C D0 08 BNE case1 0066 023E 98 TYA 0067 023F 18 CLC 0068 0240 69 80 ADC #80H 0069 0242 20 0D 02 JSR LCD_command_write 0070 0245 60 RTS 0071 0246 0072 0246 C9 01 case1 CMP #1 0073 0248 D0 08 BNE case2 0074 024A 98 TYA 0075 024B 18 CLC 0076 024C 69 C0 ADC #0C0H 0077 024E 20 0D 02 JSR LCD_command_write 0078 0251 60 RTS 0079 0252 0080 0252 60 case2 RTS 0081 0253 0082 0253 0083 0253 0084 0253 ; write ASCII code to LCD at current position 0085 0253 ; entry: A 0086 0253 0087 0253 20 03 02 putch_lcd JSR LcdReady 0088 0256 20 14 02 JSR LCD_data_write 0089 0259 60 RTS 0090 025A 0091 025A 0092 025A 0093 025A 20 24 02 main JSR InitLcd 0094 025D A9 36 LDA #'6' 0095 025F 20 53 02 JSR putch_lcd 0096 0262 A9 35 LDA #'5' 0097 0264 20 53 02 JSR putch_lcd 0098 0267 A9 30 LDA #'0' 0099 0269 20 53 02 JSR putch_lcd 0100 026C A9 32 LDA #'2' 0101 026E 20 53 02 JSR putch_lcd 0102 0271 A9 20 LDA #' ' 0103 0273 20 53 02 JSR putch_lcd 0104 0276 A9 4B LDA #'K' 0105 0278 20 53 02 JSR putch_lcd 0106 027B A9 69 LDA #'i' 0107 027D 20 53 02 JSR putch_lcd 0108 0280 A9 74 LDA #'t' 0109 0282 20 53 02 JSR putch_lcd 0110 0285 0111 0285 00 brk 0112 0286 0113 0286 0114 0286 .END 0115 0286 0116 0286 0117 0286 0118 0286 0119 0286 tasm: Number of errors = 0 15 LOGIC PROBE POWER SUPPLY The kit provides test points TP4(+5V) and TP5(GND) for using the logic probe. Students may learn digital logic signals with logic probe easily. The important signals are RESET (TP2) and PHI2 clock (TP3). Tick signal, however indicated by D1 LED blinking. Logic probe can test it at P3.7 of the 89C2051 microcontroller directly. Red clip is for +5V and Black clip for GND. + 5V at TP1 GND at TP1 16 WRITE YOUR OWN MONITOR PROGRAM The monitor ROM is U1, 27C256. Source code of the monitor program is available for download. Students can learn and modify the source code by adding more function keys, utility subroutines. The monitor program can be tested in RAM and the move to ROM chip by using the EPROM programmer. The procedure of modifying the monitor program is as follows. 1. Set the code segment to 1000h, so the hex file can be tested in RAM. 2. Use TASM with command, d:\6502\tasm -65 monitor.asm 3. The object file will be hex file, download to the kit and test run. 4. If it works fine then change code segment to 0c000h for ROM. 5. The physical address will occupy last block of 64kB space. 6. Our EPROM is 32kB, so we must move the hex code from 2nd block to the first block. Then program the EPROM. 17 HARDWARE SCHEMATIC and PARTS LIST D C B A + +5V 1 TP4 1 TP5 +5V GND A0 A1 A2 A3 A4 A5 A6 A7 C16 10uF +5V 1k 1k 1k 5 R2 IRQ RDY R3 C6 0.1uF A8 A9 A10 A11 NMI SYNC +5V R5 C5 0.1uF 5 U5 ROM_CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A0 A1 A2 A3 A4 A5 A6 A7 A[0..7] A8 A9 A10 A11 A12 A13 A14 +5V VSS RDY CLK1 IRQ NC NMI SYNC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 U1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 0xC000-0xFFFF Monitor Program 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 1 4 D0 D1 D2 D3 D4 D5 D6 D7 TP2 1 +5V A8 A9 A10 A11 A12 A13 A14 4.7k R4 A[0..7] A0 A1 A2 A3 A4 A5 A6 A7 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 U2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 BREAK 3 3 A0 A1 C4 + SYNC TXD 12 13 14 15 16 17 18 19 U3 P3.0/RXD P3.1/TXD P3.2/INTO P3.3/INT1 P3.4/T0 P3.5/T1 XTAL1 XTAL2 RST/VPP VCC AT89C2051 QA QB QC QD QE QF QG QH J1 1 2 D[0..7] 12 13 14 15 16 17 18 19 11 IRQ RESET1 user SW4 RAM_WR ROM_CE RAM_CE P3.7 P1.0/AIN0 P1.1/AIN1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 DC Input 2 2 TP1 1 TEST POINT TICK/2 TICK 1 3 U7B 74LS14 3 Title Size B Date: +5V R1 680 LED D1 VCC D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 +5V + JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 +5V R6 10k C2 10uF 1 1 1 +5V BE RDY SYNC PHI2 1MHz of VCC 3 VCC D0 D1 D2 D3 D4 D5 D6 D7 NMI IRQ RESET2 RESET1 R/W A15 A14 A13 A12 D0 D1 D2 D3 D4 D5 D6 D7 VDD VSS RESET SW3 HEADER 20X2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 CPU expansion connector 5 TVS5V_SOD123 D2 U7C TICK 10ms Tick SW2 IRQ 6 74LS14 6502 MICROPROCESSOR KIT Document Number <Doc> Saturday, January 03, 2015 Sheet Designed by Wichit Sirichote, [email protected], 2014 LCD_E PORT0 PORT1 PORT2 GPIO1 SW1 ESP switch 2 RESET2 4 IRQ test switch Programmable system tick 5 4 2 3 6 7 8 9 PHI2 1 +5V 20 RESET2 U4 I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q U6 A B CLK CLR 1 74HC164 1 3 4 5 6 10 11 12 13 PLD decoder logic I I I I I I I I I/CLK I/OE D3 74LS14 U7A 9 8 1 2 GAL16V8D 2 2 1N4007 1000uF25V +5V 2 3 4 5 6 7 8 9 8 1MHz Y1-OSC-1M-MEC1 OUT OSC14 TP3 1 1 TEST POINT VIN U8 LM2490-5.0 C11 0.1uF NMI PHI2 R/W A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 0x0000-0x7FFF 32kB SRAM, NVRAM RAM_CE 20 22 27 VOUT PHI2 RAM_WR 3 1 11 CE OE WE TEST POINT PHI2 1MHz R/W A15 C10 0.1uF A0 A1 HM62256B A[8..14] C3 + RESET1 A14 A13 A12 BE C9 0.1uF 10uF 16V D0 D1 D2 D3 D4 D5 D6 D7 27C256 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CE OE VPP RES CLK2 S0 CLK0 BE NC R/W D0 D1 D2 D3 D4 D5 D6 D7 A15 A14 A13 A12 VSS C8 0.1uF 65C02 CMOS CPU C7 0.1uF 4 GND 2 + C1 22uF Rev D C B A D C B A D0 D1 D2 D3 D4 D5 D6 D7 RESET2 5 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 + VCC 2 3 4 5 6 7 8 9 11 1 20 1 19 18 17 16 15 14 13 12 11 20 11 1 2 3 4 5 6 7 8 9 C17 10uF VCC VCC U11 1D 2D 3D 4D 5D 6D 7D 8D LE OE VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 0x01 74HC573 U12 1D 2D 3D 4D 5D 6D 7D 8D LE OE A1 A2 A3 A4 A5 A6 A7 A8 U13 74HC573 VCC TXD Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 G1 G2 VCC 74HC541 VCC 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 9 20 VCC E G F A B C DP D 4 RXD S19 PC7 SPEAKER PA0 PA1 PA2 PA3 PA4 PA5 PA6 C18 100nF 4 PC0 PC1 PC2 PC3 PC4 PC5 PC6 A B C D E F G DP 14 16 13 3 5 11 15 7 U9 A B C D E F G DP LTC-4727JR PC5 PC4 PC3 PC2 PC1 PC0 S1 S7 S13 S20 S26 S30 BREAK 3 S2 S8 S14 S21 S27 S31 3 S3 S9 S15 S22 S28 S32 2 14 16 13 3 5 11 15 7 U10 A B C D E F G DP S6 A B C D E F G DP S5 S12 4 S4 S11 S18 L1L2L3 LTC-4727JR S10 S17 S25 R7 C VCC 1 R9 330 VCC R8 4.7k D4 1 C R11 10 R10 Q1 BC327 7-segment test 2 10k RESISTOR SIP 9 2 3 4 5 6 7 8 9 TONE PA0 PA1 PA2 PA3 PA4 PA5 PA6 6502 MICROPROCESSOR KIT Document Number <Doc> Saturday, January 03, 2015 1 Sheet 2 J2 4 CON3 1 2 3 L1L2L3 LS1 3 VCC SPEAKER +5V 1 of Designed by Wichit Sirichote, [email protected], 2014 Date: Size B Title SPEAKER 10k RESISTOR SIP 9 PC0 2 PC1 3 PC2 4 PC3 5 PC4 6 PC5 7 8 9 S16 S24 S33 S29 S23 2 DIGIT4 8 D0 D1 D2 D3 D4 D5 D6 D7 PORT2 PORT1 PORT0 +5V 5 1 3 DIGIT3 6 DIGIT2 2 DIGIT1 1 DIGIT4 8 DIGIT3 6 DIGIT2 2 DIGIT1 1 Rev 1 D C B A 10 +5V 1 D0 D1 D2 D3 D4 D5 D6 D7 R13 10K A1 A0 3 VCC LCD_E 2 3 4 5 6 7 8 9 11 1 20 A1 VCC U14 1D 2D 3D 4D 5D 6D 7D 8D LE OE VCC 74HC573 A0 4 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q +5V 19 18 17 16 15 14 13 12 D5 D6 LED D7 D8 D9 3 1N5236A D13 LED D10 8-bit Binary display LED x8 VB1 3 D11 +5V D12 14 7 13 8 6 2 10uF 10V C12 C14 10uF SUB-D 9, Male (cross cable) 5 9 4 8 3 7 2 6 1 + 5 D0 D1 D2 D3 D4 D5 D6 D7 GPIO1 R12 D7 D6 D5 D4 D3 D2 D1 D0 R/W RS +5V VCC + D0 D1 D2 D3 D4 D5 D6 D7 RESET2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16x2 text LCD interface JR1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CONN RECT 16 +5V VCC 4 U15 V+ V- T1OUT T2OUT R1IN R2IN MAX232A C+ C1C2+ C2T1IN T2IN R1OUT R2OUT +5V 10uF 1 3 4 5 11 10 12 9 C19 100nF C13 + D C B A 5 2 2 C15 10uF 2 RXD TXD Title Size B 6502 MICROPROCESSOR KIT Document Number <Doc> Saturday, January 03, 2015 1 1 Sheet 3 of Designed by Wichit Sirichote, [email protected], 2014 Date: 3 D C B A Rev <RevCode> + PARTS LIST Semiconductors C4 1000uF25V electrolytic C5,C6,C7,C8,C9 0.1uF disc ceramic C10,C11 0.1uF disc ceramic C12 10uF 10V electrolytic C19,C18 100nF disc ceramic U1 27C256, 32kB EPROM U2 HM62256B, 32kB Static RAM U3 AT89C2051, 20-pin DIP microcontroller Additional parts U4 GAL16V8D, programmable logic device U5 65SC02 CMOS CPU JJP1 HEADER 20X2 U6 74HC164, shift register JR1 CONN RECT 16 text LCD connector U7 74LS14, inverter J1 DC Input U8 LM2490-5.0, voltage regulator J2 CON3 3-pin header U10,U9 LTC-4727JR, seven segment LED LS1 SPEAKER U11,U12,U14 74HC573, data latch U13 74HC541, tristate buffer U15 MAX232A, RS232 level converter SW1 ESP switch D1,D5,D6,D7,D8,D9,D10, 3mm LED SW2 IRQ D11,D12 SW3 RESET D2 TVS5V_SOD123 transient voltage suppressor SW4 user S1,S2,S3,S4,S5,S6,S7,S8, D3 1N4007 rectifying diode S9,S10,S11,S12,S13,S14,Tact switch D4 3mm LED S15,S16,S17,S18,S19,S20, D13 1N5236A S21,S22,S23,S24,S25,S26, Q1 BC327 PNP transistor S27,S28,S29,S30,S31,S32, S33 Resistors (all resistors are 1/8W +/-5%) TP1,TP2,TP3 TEST POINT TP4 +5V R1 680 TP5 GND R2,R3,R5 1k R8,R4 4.7k VB1 SUB-D 9, Male (cross cable) R13,R6 10k Y1-OSC-1M-MEC1 OSC14 R11,R7 10k RESISTOR SIP 9 PCB double side plate through hole R9 330 LED cover Clear RED color acrylic plastic R12,R10 10 Keyboard sticker printable SVG file Capacitors C1 22uF electrolytic C2,C13,C14,C15,C16,C17 10uF electrolytic C3 10uF 16V electrolytic MONITOR PROGRAM LISTINGS MONITOR.LST 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 0060 0061 0062 0063 0064 0065 0066 0067 0068 0069 0070 0071 0072 0073 0074 0075 0076 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0080 0080 0080 0080 0081 0082 0083 0084 0086 0088 8/10/2015 6:21 PM ;---------------------------------------------------------------------------; Monitor program source code for 6502 Microprocessor Kit ; Written by Wichit Sirichote, [email protected] ; Copyright (c) 2015 ; ; Source code was assembled with tasm assembler ; Example of using tasm ; ; d:\tasm\tasm -65 monitor.asm ; ; The object file will be Intel hex file ready for EPROM programmer ; The physical location is the 2nd block of 64kB space. ; To program the 32kB EPROM, we must move it to the 1st block. ; ; ; ; 26 DECEMBER 2014 ; 27 DECEMBER 2014 ; -ADD OUT OF RANGE CHECK FOR RELATIVE BYTE CALCULATION ; -ADD DOWNLOAD HEX FILE TO MONITOR SOURCE ; 29 DECEMBER 2014 ; -ADD START MESSAGE ON COLD BOOT ; 30 DECEMBER 2014 ; -TEST SINGLE STEP WITH 74LS164 ; - ADD REPEAT KEY ; - LOWER REPEAT SPEED ; - REMOVE ACCUMALATOR DISPLAY ON BREAK ; 2 JANUARY 2015 ; - REMOVE BINARY DISPLAY IN REGISTER MODE ; - ADD REGISTER MODE DISPLAY FOR 10 BYTES ZERO PAGE, $00 TO $09 ; 3 JANUARY 2015 ; - PROVIDE PROGRAM COUNTER SAVING FOR SINGLE STEP RUNNING ; now user may change display address, data, to get back current address ; press PC key to restore it, then press step ; ; 27 February 2015 ; lower brightness of the 7-segment ; calibrate beep frequency to 523Hz ; 2 March 2015 ; add hex file download using MOS hex format ; now the board can accept both Intel and MOS hex file format. Tested ; no error, the GPIO1 will display 0D (CR), if error it will show 01. ; ; 21 March fix cold boot message, make beep on cold boot ; address of the I/O ports GPIO1 PORT0 PORT1 PORT2 .EQU .EQU .EQU .EQU 8000H 8001H 8002H 8003H DIGIT SEG7 KIN .EQU 8002H .EQU 8003H .EQU 8001H ; page zero register definition ; LOCATION $00 TO $7F ARE 128 BYTES FOR USER PROGRAM TESTING .DSEG .ORG 80H ; zero page memory definitions for monitor use REG_E .BLOCK 1 REG_D .BLOCK 1 REG_B .BLOCK 1 REG_C .BLOCK 1 HL .BLOCK 2 ; 84H = L 85H = H DE .BLOCK 2 REG_A .BLOCK 1 Page 1 of 28 MONITOR.LST 0077 0078 0079 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 0130 0131 0132 0133 0134 0135 0136 0137 0138 0139 0140 0141 0142 0143 0144 0145 0146 0147 0148 0149 0150 0151 0152 0089 0089 008A 008C 0092 0093 0093 0093 0093 0094 0095 0096 0096 0098 0098 009A 009B 009C 009D 009E 009F 00A0 00A0 00A2 00A4 00A6 00A7 00A7 00A8 00A9 00AA 00AA 00AC 00AC 00AC 00AC 00AC C000 C000 C000 C000 C002 C005 C007 C00A C00A C00A C00A C00C C00D C00F C00F C00F C00F C012 C012 C012 C012 C012 C014 C015 C017 C018 C018 C018 C018 C01A C01B C01D C01E C01E C01E C01E C01E C020 C020 8/10/2015 6:21 PM _ERROR BCC BUFFER INVALID .BLOCK .BLOCK .BLOCK .BLOCK 1 2 6 1 ; ERROR FLAG FOR INTEL HEX FILE DOWNLOADING ; BYTE CHECK SUM ; 8BH - 90H PAGE ZERO DISPLAY BUFFER ; INVALID KEY HAS BEEN PRESSED FLAG BIT ; 0 VALID ; 1 INVALID KEY .BLOCK 1 STATE .BLOCK 1 ZERO_FLAG .BLOCK 1 DISPLAY .BLOCK 2 PC_USER USER_A USER_X USER_Y USER_S USER_P SAVE_SP ; ZERO WHEN HEX KEY PRESSED FOR ADDRESS OR ; display address .BLOCK 2 .BLOCK 1 .BLOCK 1 .BLOCK 1 .BLOCK 1 .BLOCK 1 .BLOCK 1 START_ADDRESS .BLOCK 2 DESTINATION .BLOCK 2 OFFSET_BYTE .BLOCK 2 COLD .BLOCK 1 ; FOR SAVING CURRENT PC, ON RESET, IT SETS TO ; USER STACK POINTER ; PROGRAM STATUS REGISTER ; SAVE SYSTEM STACK ; FOR OFFSET BYTE CALCULATION ; OFFSET BYTE = DESTINATION - START_ADDRESS ; COLD BOOT OR WARM BOOT REPDELAY .BLOCK 1 SAVE_X .BLOCK 1 SAVE_Y .BLOCK 1 DEBUG .BLOCK 2 ; FOR PROGRAM DEBUGGING .CSEG ; A9 8D A9 8D BF 02 80 00 03 80 .ORG 0C000H .ORG 1000H ; START ADDRESS FOR ROM ; START ADDRESS FOR CODE TESTING IN RAM LDA #$BF ; turn off break signal STA PORT1 LDA #0 STA PORT2 ; turn of 7-segment ; power up delay A2 00 CA D0 FD LDX #0 POWER_UP_DELAY DEX BNE POWER_UP_DELAY ; jump to main code 4C 72 C8 JMP MAIN ;----------------------- 2400 BIT/S SOFTWARE UART --------------------------; one bit delay for 2400 bit/s UART A0 4C 88 D0 FD 60 BIT_DELAY LDY #76 LOOP DEY BNE LOOP RTS ; 1190 Hz TEST AT 1MHZ OSCILLATOR ; 1.5 bit delay A0 72 88 D0 FD 60 BIT1_5_DELAY LDY #114 LOOP1 DEY BNE LOOP1 RTS ; DELAY 1.5 BIT ; SEND ASCII LETTER TO TERMINAL ; ENTRY: A 85 80 A9 3F SEND_BYTE: STA REG_E LDA #3FH ; SAVE ACCUMULATOR ; start bit is zero Page 2 of 28 MONITOR.LST 0153 0154 0155 0156 0157 0158 0159 0160 0161 0162 0163 0164 0165 0166 0167 0168 0169 0170 0171 0172 0173 0174 0175 0176 0177 0178 0179 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 0190 0191 0192 0193 0194 0195 0196 0197 0198 0199 0200 0201 0202 0203 0204 0205 0206 0207 0208 0209 0210 0211 0212 0213 0214 0215 0216 0217 0218 0219 0220 0221 0222 0223 0224 0225 0226 0227 0228 C022 C025 C028 C028 C02A C02C C02C C02E C030 C032 C032 C034 C037 C037 C03A C03A C03A C03C C03F C042 C042 C045 C045 C047 C049 C04B C04B C04D C050 C053 C054 C054 C054 C054 C054 C054 C057 C059 C05B C05B C05E C05E C060 C062 C064 C066 C066 C066 C066 C069 C06B C06D C06D C06F C071 C073 C076 C076 C078 C07A C07C C07F C07F C082 C082 C084 C084 C086 C088 C088 C08B C08B C08D C08D C08E C08E 8/10/2015 6:21 PM 8D 02 80 20 12 C0 STA PORT1 JSR BIT_DELAY A9 08 85 81 LDA #8 STA REG_D A5 80 29 01 F0 08 ; delay one bit ; 8-data bit wil be sent CHK_BIT: LDA REG_E AND #1 BEQ SEND_ZERO A9 BF 8D 02 80 LDA #0BFH STA PORT1 4C 42 C0 JMP NEXT_BIT A9 3F 8D 02 80 4C 42 C0 SEND_ZERO: LDA #3FH STA PORT1 JMP NEXT_BIT 20 12 C0 NEXT_BIT: JSR BIT_DELAY 46 80 C6 81 D0 E1 LSR REG_E DEC REG_D BNE CHK_BIT A9 BF 8D 02 80 20 12 C0 60 LDA #0BFH STA PORT1 JSR BIT_DELAY RTS ; RECEIVE BYTE FROM 2400 BIT/S TERMINAL ; EXIT: A AD 01 80 29 80 D0 F9 CIN LDA PORT0 AND #80H BNE CIN 20 18 C0 JSR BIT1_5_DELAY A9 85 A9 85 LDA STA LDA STA 07 81 00 80 AD 01 80 29 80 D0 09 A5 29 85 4C 80 7F 80 7F C0 A5 09 85 4C 80 80 80 7F C0 20 12 C0 #7 REG_D #0 REG_E CHK_BIT_RX LDA PORT0 AND #80H BNE BIT_IS_ONE LDA REG_E AND #7FH STA REG_E JMP NEXT_BIT_RX BIT_IS_ONE LDA REG_E ORA #80H STA REG_E JMP NEXT_BIT_RX NEXT_BIT_RX JSR BIT_DELAY 46 80 LSR REG_E C6 81 D0 DE DEC REG_D BNE CHK_BIT_RX 20 12 C0 JSR BIT_DELAY A5 80 LDA REG_E 60 RTS ; CENTER OF STOP BIT Page 3 of 28 MONITOR.LST 0229 0230 0231 0232 0233 0234 0235 0236 0237 0238 0239 0240 0241 0242 0243 0244 0245 0246 0247 0248 0249 0250 0251 0252 0253 0254 0255 0256 0257 0258 0259 0260 0261 0262 0263 0264 0265 0266 0267 0268 0269 0270 0271 0272 0273 0274 0275 0276 0277 0278 0279 0280 0281 0282 0283 0284 0285 0286 0287 0288 0289 0290 0291 0292 0293 0294 0295 0296 0297 0298 0299 0300 0301 0302 0303 0304 C08E C08E C08E C08E C091 C093 C095 C096 C096 C099 C09A C09D C09D C09D C09D C09D C09D C09D C09D C09D C09F C0A2 C0A4 C0A7 C0A8 C0A8 C0A8 C0A8 C0AA C0AB C0AD C0AF C0B1 C0B2 C0B4 C0B7 C0B8 C0B8 C0B8 C0B9 C0B9 C0BA C0BB C0BC C0BD C0BD C0BD C0BD C0C0 C0C1 C0C4 C0C5 C0C5 C0C5 C0C5 C0C5 C0C5 C0C6 C0C8 C0CA C0CC C0CE C0D0 C0D2 C0D3 C0D3 C0D3 C0D3 C0D3 C0D6 C0D8 C0DA C0DA C0DA C0DA C0DC 8/10/2015 6:21 PM ; PRINT TEXT FROM STRING AREA ; ENTRY: X POINTED TO OFFSET BD 00 EF C9 00 D0 01 60 PSTRING LDA TEXT1,X CMP #0 BNE PRINT_IT RTS 20 1E C0 E8 4C 8E C0 PRINT_IT JSR SEND_BYTE INX JMP PSTRING CR LF EOS .EQU 0DH .EQU 0AH .EQU 0 ;NEW LINE ; PRINT CR, LF A9 20 A9 20 60 0D 1E C0 0A 1E C0 29 18 69 C9 90 18 69 20 60 0F 30 3A 03 07 1E C0 48 NEW_LINE LDA #0DH JSR SEND_BYTE LDA #0AH JSR SEND_BYTE RTS ; WRITE NIBBLE TO TERMINAL OUT1X AND #0FH CLC ADC #30H CMP #3AH BCC OUT1X1 CLC ADC #7 OUT1X1 JSR SEND_BYTE RTS OUT2X 4A 4A 4A 4A PHA LSR A LSR A LSR A LSR A ; 20 A8 C0 68 20 A8 C0 60 STA GPIO1 JSR OUT1X PLA JSR OUT1X RTS ; INCREMENT HL ; INCREMENT 16-BIT POINTER FOR 16-BIT MEMORY ACCESS 18 A5 69 85 A5 69 85 60 INC_HL 84 01 84 85 00 85 ADC STA LDA ADC STA RTS CLC LDA HL #1 HL HL+1 #0 HL+1 ; PRINT LINE OF MEMORY POINTED TO HL 20 9D C0 A9 10 85 83 A5 85 20 B8 C0 PRINT_LINE JSR NEW_LINE LDA #16 STA REG_C LDA HL+1 JSR OUT2X Page 4 of 28 MONITOR.LST 0305 0306 0307 0308 0309 0310 0311 0312 0313 0314 0315 0316 0317 0318 0319 0320 0321 0322 0323 0324 0325 0326 0327 0328 0329 0330 0331 0332 0333 0334 0335 0336 0337 0338 0339 0340 0341 0342 0343 0344 0345 0346 0347 0348 0349 0350 0351 0352 0353 0354 0355 0356 0357 0358 0359 0360 0361 0362 0363 0364 0365 0366 0367 0368 0369 0370 0371 0372 0373 0374 0375 0376 0377 0378 0379 0380 C0DF C0E1 C0E4 C0E4 C0E6 C0E9 C0E9 C0EB C0ED C0ED C0F0 C0F0 C0F2 C0F5 C0F5 C0F8 C0F8 C0FA C0FA C0FC C0FC C0FD C0FD C0FD C0FD C0FD C0FE C100 C102 C104 C106 C107 C109 C109 C10A C10A C10A C10A C10A C10D C110 C111 C112 C113 C114 C114 C117 C117 C119 C119 C11C C11F C120 C122 C122 C123 C123 C123 C123 C123 C126 C127 C12A C12B C12E C12F C130 C131 C132 C132 C135 C135 C137 C137 C13A C13B 8/10/2015 6:21 PM A5 84 20 B8 C0 LDA HL JSR OUT2X A9 3A 20 1E C0 LDA #':' JSR SEND_BYTE A0 00 B1 84 PRINT_LINE2 LDY #0 LDA (HL),Y 20 B8 C0 JSR OUT2X A9 20 20 1E C0 LDA #' ' JSR SEND_BYTE 20 C5 C0 JSR INC_HL C6 83 DEC REG_C D0 ED BNE PRINT_LINE2 60 RTS ; CONVERT ASCII TO HEX ; ENTRY: A 38 E9 C9 90 29 38 E9 TO_HEX 30 10 05 DF 07 60 SEC SBC #30H CMP #10H BCC ZERO_NINE AND #11011111B SEC SBC #7 ZERO_NINE RTS ; CONVERT TWO ASCII LETTERS ; EXIT: A 20 54 C0 20 FD C0 0A 0A 0A 0A GET_HEX JSR CIN JSR TO_HEX ASL A ASL A ASL A ASL A 8D 00 80 STA GPIO1 85 88 STA REG_A 20 54 C0 20 FD C0 18 65 88 JSR CIN JSR TO_HEX CLC ADC REG_A 60 RTS ; CONVERT TWO ASCII LETTERS ; EXIT: A 20 54 C0 48 20 1E C0 68 20 FD C0 0A 0A 0A 0A TO SINGLE BYTE GET_HEX2 TO SINGLE BYTE JSR CIN PHA JSR SEND_BYTE ; ECHO TO TERMINAL PLA JSR TO_HEX ASL A ASL A ASL A ASL A 8D 00 80 STA GPIO1 85 88 STA REG_A 20 54 C0 48 20 1E C0 JSR CIN PHA JSR SEND_BYTE Page 5 of 28 MONITOR.LST 0381 0382 0383 0384 0385 0386 0387 0388 0389 0390 0391 0392 0393 0394 0395 0396 0397 0398 0399 0400 0401 0402 0403 0404 0405 0406 0407 0408 0409 0410 0411 0412 0413 0414 0415 0416 0417 0418 0419 0420 0421 0422 0423 0424 0425 0426 0427 0428 0429 0430 0431 0432 0433 0434 0435 0436 0437 0438 0439 0440 0441 0442 0443 0444 0445 0446 0447 0448 0449 0450 0451 0452 0453 0454 0455 0456 C13E C13F C142 C143 C145 C145 C146 C146 C146 C146 C146 C149 C14B C14E C151 C153 C156 C158 C159 C159 C15A C15C C15E C15F C15F C15F C15F C15F C161 C163 C163 C166 C168 C16A C16A C16C C16E C16E C171 C171 C171 C171 C171 C173 C175 C175 C178 C17A C17A C17D C17D C180 C182 C182 C185 C185 C188 C18A C18A C18D C18D C190 C190 C192 C192 C194 C194 C197 C199 C19B C19B C19E C19E C1A0 C1A2 C1A4 8/10/2015 6:21 PM 68 20 FD C0 18 65 88 PLA JSR TO_HEX CLC ADC REG_A 60 RTS ;----------------------------------------------------SET_NEW_ADDRESS 20 A2 20 20 85 20 85 60 1E 1C 8E 23 85 23 84 C0 C0 C1 C1 18 65 8A 85 8A 60 JSR SEND_BYTE LDX #PROMPT&00FFH JSR PSTRING JSR GET_HEX2 STA HL+1 JSR GET_HEX2 STA HL RTS ADD_BCC CLC ADC BCC STA BCC RTS ;--------------------------------------------------------; GET_RECORD READS INTEL HEX FILE AND SAVE TO MEMORY A9 00 85 89 GET_RECORD LDA #0 STA _ERROR 20 54 C0 C9 3A F0 07 GET_RECORD1 JSR CIN CMP #':' BEQ GET_RECORD2 C9 3B D0 F5 CMP #$3B BNE GET_RECORD1 4C ED C1 JMP GET_MOS2 ; ';' GET_RECORD2 A9 00 85 8A LDA #0 STA BCC 20 0A C1 85 83 JSR GET_HEX STA REG_C 20 59 C1 JSR ADD_BCC 20 0A C1 85 85 JSR GET_HEX STA HL+1 20 59 C1 JSR ADD_BCC 20 0A C1 85 84 JSR GET_HEX STA HL 20 59 C1 JSR ADD_BCC 20 0A C1 JSR GET_HEX C9 00 CMP #0 F0 14 BEQ DATA_RECORD 20 54 C0 C9 0D D0 F9 ; GET NUMBER OF BYTE ; GET LOAD ADDRESS WAIT_CR JSR CIN CMP #0DH BNE WAIT_CR 8D 00 80 STA GPIO1 A5 89 C9 01 D0 03 LDA _ERROR CMP #1 BNE NOERROR Page 6 of 28 MONITOR.LST 0457 0458 0459 0460 0461 0462 0463 0464 0465 0466 0467 0468 0469 0470 0471 0472 0473 0474 0475 0476 0477 0478 0479 0480 0481 0482 0483 0484 0485 0486 0487 0488 0489 0490 0491 0492 0493 0494 0495 0496 0497 0498 0499 0500 0501 0502 0503 0504 0505 0506 0507 0508 0509 0510 0511 0512 0513 0514 0515 0516 0517 0518 0519 0520 0521 0522 0523 0524 0525 0526 0527 0528 0529 0530 0531 0532 C1A4 C1A4 C1A4 C1A4 C1A7 C1A7 C1A7 C1A8 C1A8 C1A8 C1A8 C1AB C1AD C1AF C1AF C1B2 C1B2 C1B5 C1B5 C1B8 C1B8 C1BA C1BC C1BC C1BE C1C0 C1C1 C1C3 C1C5 C1C5 C1C5 C1C8 C1C8 C1CA C1CC C1CC C1CE C1D0 C1D0 C1D0 C1D0 C1D0 C1D3 C1D3 C1D3 C1D3 C1D3 C1D3 C1D6 C1D8 C1DB C1DD C1E0 C1E0 C1E0 C1E2 C1E5 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E6 C1E9 8/10/2015 6:21 PM ; SHOW ERROR ON LED ; JSR OUT_OFF_RANGE 8D 00 80 STA GPIO1 NOERROR 60 RTS DATA_RECORD 20 0A C1 A0 00 91 84 JSR GET_HEX LDY #0 STA (HL),Y ; WRITE TO MEMORY 20 59 C1 JSR ADD_BCC 8D 00 80 STA GPIO1 20 C5 C0 JSR INC_HL C6 83 D0 EC DEC REG_C BNE DATA_RECORD ; UNTIL C=0 A5 49 18 69 85 LDA BCC EOR #0FFH ; ONE'S COMPLEMENT CLC ADC #1 ; TWO'S COMPLEMENT STA BCC 8A FF 01 8A 20 0A C1 JSR GET_HEX ; GET BYTE CHECK SUM C5 8A F0 04 CMP BCC ; COMPARE WITH BYTE CHECK SUM BEQ SKIP11 A9 01 85 89 LDA #1 STA _ERROR ; ERROR FLAG =1 SKIP11 4C 63 C1 JMP GET_RECORD1 ; NEXT LINE SEND_PROMPT 20 A5 20 A5 20 9D C0 85 B8 C0 84 B8 C0 A2 1C 20 8E C0 60 JSR NEW_LINE LDA HL+1 JSR OUT2X LDA HL JSR OUT2X LDX #PROMPT&00FFH JSR PSTRING RTS ;=================================================================== ; get MOS record ; sample MOS record ; ;18 0200 A9018500182600A5008D0080A200A00088D0FDCAD0F84C05 09B3 ;01 0218 02 001D ;00 ; ; 18 is number of byte ; 0200 is load address ; A9, 01, 85.. data byte ; 09B3 is 16-bit check sum GET_MOS1 20 54 C0 C9 3B JSR CIN CMP #$3B ; ';' Page 7 of 28 MONITOR.LST 0533 0534 0535 0536 0537 0538 0539 0540 0541 0542 0543 0544 0545 0546 0547 0548 0549 0550 0551 0552 0553 0554 0555 0556 0557 0558 0559 0560 0561 0562 0563 0564 0565 0566 0567 0568 0569 0570 0571 0572 0573 0574 0575 0576 0577 0578 0579 0580 0581 0582 0583 0584 0585 0586 0587 0588 0589 0590 0591 0592 0593 0594 0595 0596 0597 0598 0599 0600 0601 0602 0603 0604 0605 0606 0607 0608 C1EB C1ED C1ED C1ED C1ED C1EF C1F1 C1F3 C1F3 C1F3 C1F6 C1F8 C1F8 C1FA C1FC C1FC C1FF C1FF C202 C204 C204 C207 C207 C20A C20C C20C C20F C20F C212 C212 C215 C217 C219 C219 C21C C21C C21E C220 C222 C222 C222 C222 C225 C225 C225 C225 C226 C226 C226 C226 C229 C22B C22D C22D C230 C230 C233 C233 C236 C236 C238 C23A C23A C23A C23A C23D C23F C23F C23F C242 C244 C244 C244 C246 C248 C24A 8/10/2015 6:21 PM D0 F9 BNE GET_MOS1 GET_MOS2 A9 00 85 8A 85 8B LDA #0 STA BCC STA BCC+1 20 0A C1 85 83 JSR GET_HEX STA REG_C C9 00 F0 16 CMP #0 BEQ END_RECORD 20 5A C2 JSR ADD_BCC_MOS 20 0A C1 85 85 JSR GET_HEX STA HL+1 20 5A C2 JSR ADD_BCC_MOS 20 0A C1 85 84 JSR GET_HEX STA HL 20 5A C2 JSR ADD_BCC_MOS 4C 26 C2 JMP DATA_RECORD2 20 54 C0 C9 0D D0 F9 ; MOS uses 16-bit checksum ; GET NUMBER OF BYTE ; GET LOAD ADDRESS END_RECORD JSR CIN CMP #0DH BNE END_RECORD 8D 00 80 STA GPIO1 A5 89 C9 01 D0 03 LDA _ERROR CMP #1 BNE NOERROR2 ; SHOW ERROR ON LED 8D 00 80 STA GPIO1 NOERROR2 60 RTS DATA_RECORD2 20 0A C1 A0 00 91 84 JSR GET_HEX LDY #0 STA (HL),Y ; WRITE TO MEMORY 20 5A C2 JSR ADD_BCC_MOS 8D 00 80 STA GPIO1 20 C5 C0 JSR INC_HL C6 83 D0 EC DEC REG_C BNE DATA_RECORD2 ; UNTIL C=0 ; now get 16-bit check sum 20 0A C1 85 85 ; JSR GET_HEX STA HL+1 STA DEBUG+1 ; GET 16-bit CHECK SUM 20 0A C1 85 84 JSR GET_HEX STA HL ; check sum now stored in HL+1 and HL ; STA DEBUG A5 C5 D0 A5 LDA CMP BNE LDA 8B 85 09 8A BCC+1 HL+1 error_mos BCC Page 8 of 28 MONITOR.LST 0609 0610 0611 0612 0613 0614 0615 0616 0617 0618 0619 0620 0621 0622 0623 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 0652 0653 0654 0655 0656 0657 0658 0659 0660 0661 0662 0663 0664 0665 0666 0667 0668 0669 0670 0671 0672 0673 0674 0675 0676 0677 0678 0679 0680 0681 0682 0683 0684 C24C C24E C250 C250 C253 C253 C253 C255 C257 C257 C257 C257 C257 C25A C25A C25A C25A C25A C25A C25A C25B C25D C25F C261 C263 C265 C266 C266 C266 C266 C266 C266 C266 C266 C266 C266 C268 C26A C26C C26C C26E C270 C270 C270 C272 C272 C274 C274 C276 C279 C279 C27C C27F C27F C281 C282 C284 C284 C286 C289 C289 C289 C289 C289 C28A C28A C28C C28D C28F C28F C291 C293 C293 C295 C295 C296 8/10/2015 6:21 PM C5 84 D0 03 CMP HL BNE error_mos 4C 57 C2 JMP SKIP12 A9 01 85 89 error_mos LDA #1 STA _ERROR ; ERROR FLAG =1 SKIP12 4C E6 C1 JMP GET_MOS1 ; NEXT LINE ; add 16-bit check sum, stores in BCC+1 and BCC ADD_BCC_MOS 18 65 85 A9 65 85 60 8A 8A 00 8B 8B CLC ADC BCC STA LDA ADC STA RTS BCC #0 BCC+1 BCC+1 ;--------------------------------- END UART CODE ---------------------------; SCAN DISPLAY ONLY ; ENTRY: X POINTED TO NEXT MESSAGE BYTE ; FIX_MESSAGE LOCATION 86 83 A9 01 85 80 SCAN2: STX REG_C LDA #1 STA REG_E A9 06 85 84 LDA #6 STA HL A5 80 ;to the active column. KCOL2 LDA REG_E 49 FF EOR #0FFH 29 BF 8D 02 80 AND #0BFH STA DIGIT BD E3 C8 8D 03 80 LDA START_MSG,X STA SEG7 A0 05 88 D0 FD LDY #$5 DELAY5 DEY BNE DELAY5 A9 00 8D 03 80 LDA #0 STA SEG7 E8 INX A5 80 0A 85 80 LDA REG_E ASL A STA REG_E C6 84 D0 DD DEC BNE A6 83 LDX REG_C 60 RTS ; COMPLEMENT IT ; BREAK MUST BE LOGIC '0' TO DISABLE ; TURN LED OFF HL KCOL2 Page 9 of 28 MONITOR.LST 0685 0686 0687 0688 0689 0690 0691 0692 0693 0694 0695 0696 0697 0698 0699 0700 0701 0702 0703 0704 0705 0706 0707 0708 0709 0710 0711 0712 0713 0714 0715 0716 0717 0718 0719 0720 0721 0722 0723 0724 0725 0726 0727 0728 0729 0730 0731 0732 0733 0734 0735 0736 0737 0738 0739 0740 0741 0742 0743 0744 0745 0746 0747 0748 0749 0750 0751 0752 0753 0754 0755 0756 0757 0758 0759 0760 C296 C296 C296 C296 C296 C296 C296 C296 C296 C296 C296 C298 C298 C29A C29C C29C C29E C2A0 C2A0 C2A2 C2A4 C2A4 C2A6 C2A8 C2A8 C2A8 C2AA C2AA C2AC C2AE C2AE C2B1 C2B1 C2B3 C2B6 C2B6 C2B8 C2B9 C2BB C2BB C2BD C2C0 C2C0 C2C2 C2C3 C2C5 C2C5 C2C5 C2C7 C2C9 C2C9 C2CC C2CC C2CE C2CE C2CE C2D0 C2D0 C2D2 C2D2 C2D4 C2D6 C2D6 C2D8 C2D8 C2DA C2DC C2DC C2DD C2DD C2DF C2E0 C2E2 C2E2 C2E2 C2E4 8/10/2015 6:21 PM ; ; ; ; ; SCAN DISPLAY AND KEYBOARD ENTRY: DISPLAY BUFFER IN PAGE 0 EXIT: KEY = -1 NO KEY PRESSED KEY >=0 KEY POSITION REGSITERS USED: X,A,Y SCAN1: A2 00 LDX #0 A9 00 85 83 LDA #0 STA REG_C A9 FF 85 93 LDA #-1 STA KEY A9 01 85 80 LDA #1 STA REG_E A9 06 85 84 LDA #6 STA HL A5 80 ;to the active column. KCOL LDA REG_E 49 FF 29 BF EOR #0FFH AND #0BFH 8D 02 80 STA DIGIT B5 8C 8D 03 80 LDA BUFFER,X STA SEG7 A0 30 88 D0 FD LDY #$30 DELAY3 DEY BNE DELAY3 A9 00 8D 03 80 LDA #0 STA SEG7 A0 32 88 D0 FD LDY #50 DELAY10 DEY BNE DELAY10 A9 06 85 82 LDA #6 STA REG_B AD 01 80 LDA KIN 85 81 STA 46 81 B0 04 KROW LSR REG_D ;Rotate D 1 bit right, bit 0 ;of D will be rotated into BCS NOKEY ;carry flag. A5 83 85 93 LDA REG_C STA KEY E6 83 NOKEY INC REG_C C6 82 D0 F2 DEC REG_B BNE KROW E8 INX A5 80 0A 85 80 LDA REG_E ASL A STA REG_E C6 84 D0 C2 DEC BNE ; COMPLEMENT IT ; MUST BE LOW FOR BREAK ; TURN LED OFF REG_D ;Increase current key-code by 1. HL KCOL Page 10 of 28 MONITOR.LST 0761 0762 0763 0764 0765 0766 0767 0768 0769 0770 0771 0772 0773 0774 0775 0776 0777 0778 0779 0780 0781 0782 0783 0784 0785 0786 0787 0788 0789 0790 0791 0792 0793 0794 0795 0796 0797 0798 0799 0800 0801 0802 0803 0804 0805 0806 0807 0808 0809 0810 0811 0812 0813 0814 0815 0816 0817 0818 0819 0820 0821 0822 0823 0824 0825 0826 0827 0828 0829 0830 0831 0832 0833 0834 0835 0836 C2E6 C2E7 C2E7 C2E7 C2E9 C2EA C2EC C2ED C2ED C2ED C2ED C2F0 C2F2 C2F4 C2F6 C2F6 C2F9 C2FB C2FD C2FD C2FD C2FF C301 C301 C304 C306 C308 C308 C308 C30A C30C C30C C30C C30F C30F C30F C30F C312 C314 C316 C318 C318 C31B C31B C31E C31E C320 C321 C324 C324 C324 C325 C325 C325 C325 C325 C325 C325 C325 C326 C329 C32A C32A C32A C32A C32A C32A C32A C32B C32D C330 C332 C333 C334 C335 C336 8/10/2015 6:21 PM 60 RTS A0 C8 88 D0 FD 60 DEBOUNCE LDY #200 DELAY4 DEY BNE DELAY4 RTS ;-------------------------------------------------------------------- 20 A5 C9 F0 96 C2 93 FF 16 SCANKEY JSR SCAN1 LDA KEY CMP #-1 BEQ KEY_RELEASED AD 01 80 29 40 D0 F0 LDA PORT0 AND #40H BNE SCANKEY A9 20 85 A7 ; IF REPEAT KEY WAS PRESSED, SLOW DOWN IT LDA #20H STA REPDELAY 20 96 C2 C6 A7 D0 F9 DISPLAY4 JSR SCAN1 DEC REPDELAY BNE DISPLAY4 A2 00 86 92 LDX #0 STX INVALID KEY_RELEASED 20 E7 C2 JSR DEBOUNCE ; THEN REPEAT KEY PRESS ; RESET INVALID FLAG UNTIL_PRESS 20 A5 C9 F0 96 C2 93 FF F7 JSR SCAN1 LDA KEY CMP #-1 BEQ UNTIL_PRESS 20 E7 C2 JSR DEBOUNCE 20 96 C2 JSR SCAN1 A5 93 AA BD FF C8 LDA KEY TAX LDA KEYTAB,X 60 ;STA GPIO1 RTS ; OPEN TABLE ; TEST NOW A IS INTERNAL CODE ; CONVERT LOW NIBBLE IN ACCUMULATOR TO 7-SEGMENT PATTERN ; ENTRY: A ; EXIT: A NIBBLE_7SEG AA BD EF C8 60 TAX LDA SEGTAB,X RTS ; CONVERT BYTE TO 7-SEGMENT PATTERN ; ENTRY: A ; EXIT: DE 48 29 0F 20 25 C3 85 86 68 4A 4A 4A 4A BYTE_7SEG PHA AND #0FH JSR NIBBLE_7SEG STA DE PLA LSR A LSR A LSR A LSR A Page 11 of 28 MONITOR.LST 0837 0838 0839 0840 0841 0842 0843 0844 0845 0846 0847 0848 0849 0850 0851 0852 0853 0854 0855 0856 0857 0858 0859 0860 0861 0862 0863 0864 0865 0866 0867 0868 0869 0870 0871 0872 0873 0874 0875 0876 0877 0878 0879 0880 0881 0882 0883 0884 0885 0886 0887 0888 0889 0890 0891 0892 0893 0894 0895 0896 0897 0898 0899 0900 0901 0902 0903 0904 0905 0906 0907 0908 0909 0910 0911 0912 C337 C33A C33C C33D C33D C33D C33D C33D C33E C341 C343 C345 C347 C349 C34A C34B C34B C34B C34B C34B C34B C34B C34D C350 C352 C354 C356 C358 C35A C35D C35F C361 C363 C365 C366 C366 C366 C366 C366 C366 C366 C366 C368 C36A C36A C36A C36A C36A C36C C36E C36E C370 C372 C372 C374 C377 C377 C379 C37B C37E C37E C380 C382 C385 C385 C387 C389 C38C C38C C38E C390 C393 C393 C395 C397 C39A 8/10/2015 6:21 PM 20 25 C3 85 87 60 JSR NIBBLE_7SEG STA DE+1 RTS ; CONVERT BYTE TO 7-SEGMENT PATTERN AND SAVE TO DISPLAY BUFFER DATA FIELD ; ENTRY: A 48 20 A5 85 A5 85 68 60 2A C3 86 8C 87 8D DATA_DISPLAY PHA ; SAVE ACCUMULATOR JSR BYTE_7SEG LDA DE STA BUFFER LDA DE+1 STA BUFFER+1 PLA RTS ; CONVERT 16-BIT ADDRESS IN HL AND SAVE IT TO ADDRESS FILED DISPLAY BUFFER ; ENTRY: HL ADDRESS_DISPLAY A5 20 A5 85 A5 85 A5 20 A5 85 A5 85 60 84 2A C3 86 8E 87 8F 85 2A C3 86 90 87 91 JSR LDA STA LDA STA LDA JSR LDA STA LDA STA RTS LDA HL BYTE_7SEG DE BUFFER+2 DE+1 BUFFER+3 HL+1 BYTE_7SEG DE BUFFER+4 DE+1 BUFFER+5 ;**************************************************************************** ; ; EXECUTE FUNCTIONS OR HEX KEY ENTERED ; CHECK HEX KEY OR FUNCTIONS KEY ; ENTRY: A C9 10 B0 41 KEYEXE CMP #10H BCS FUNCTION_KEY ;HHHHHHHHHHHHHHH KEY HEX ENTERED HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH 85 83 A5 94 STA REG_C LDA STATE C9 01 D0 05 CMP #1 BNE CHK_STATE2 A5 83 4C 1C C5 LDA REG_C JMP HEX_ADDR ; SAVE HEX KEY C9 02 D0 03 4C 4A C5 CHK_STATE2 CMP #2 BNE CHK_STATE3 JMP HEX_DATA C9 03 D0 03 4C 23 C7 CHK_STATE3 CMP #3 BNE CHK_STATE5 JMP HEX_REG C9 05 D0 03 4C 04 C5 CHK_STATE5 CMP #5 BNE CHK_STATE6 JMP HEX_REL C9 06 D0 03 4C 10 C5 CHK_STATE6 CMP #6 BNE CHK_STATE7 JMP HEX_REL6 C9 07 D0 03 4C EC C4 CHK_STATE7 CMP #7 BNE CHK_STATE8 JMP HEX_SEND_FILE Page 12 of 28 MONITOR.LST 0913 0914 0915 0916 0917 0918 0919 0920 0921 0922 0923 0924 0925 0926 0927 0928 0929 0930 0931 0932 0933 0934 0935 0936 0937 0938 0939 0940 0941 0942 0943 0944 0945 0946 0947 0948 0949 0950 0951 0952 0953 0954 0955 0956 0957 0958 0959 0960 0961 0962 0963 0964 0965 0966 0967 0968 0969 0970 0971 0972 0973 0974 0975 0976 0977 0978 0979 0980 0981 0982 0983 0984 0985 0986 0987 0988 C39A C39C C39E C3A1 C3A1 C3A3 C3A6 C3A8 C3AA C3AA C3AA C3AA C3AA C3AA C3AA C3AA C3AA C3AB C3AB C3AB C3AB C3AB C3AB C3AD C3AF C3B2 C3B2 C3B4 C3B6 C3B9 C3B9 C3BB C3BD C3C0 C3C0 C3C2 C3C4 C3C7 C3C7 C3C9 C3CB C3CE C3CE C3D0 C3D2 C3D5 C3D5 C3D7 C3D9 C3DC C3DC C3DE C3E0 C3E3 C3E3 C3E5 C3E7 C3EA C3EA C3EC C3EE C3F1 C3F1 C3F1 C3F3 C3F5 C3F8 C3F8 C3FA C3FC C3FF C400 C400 C400 C400 C401 8/10/2015 6:21 PM C9 08 D0 03 4C F8 C4 CHK_STATE8 A5 8D A9 85 CHK_STATE9 83 00 80 01 92 CMP #8 BNE CHK_STATE9 JMP HEX_SEND_FILE2 lda REG_C sta GPIO1 LDA #1 STA INVALID ; INVALID KEY PRESSED ; HEX KEY WAS PRESSED 60 RTS ;FFFFFFFFFFFFFFFFFFFFFF FUNCTION KEY FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FUNCTION_KEY C9 19 D0 03 4C 79 C4 CMP #19H BNE CHK_FUNC1 JMP KEY_ADDR ; KEY ADDR C9 14 D0 03 4C A9 C4 CHK_FUNC1 CMP #14H ; KEY DATA BNE CHK_FUNC2 JMP KEY_DATA C9 10 D0 03 4C 6A C5 CHK_FUNC2 CMP #10H ; KEY + BNE CHK_FUNC3 JMP KEY_INC C9 11 D0 03 4C C5 C5 CHK_FUNC3 CMP #11H ; KEY BNE CHK_FUNC4 JMP KEY_DEC C9 18 D0 03 4C DE C5 CHK_FUNC4 C9 1B D0 03 4C F2 C5 CHK_FUNC5 C9 12 D0 03 4C 43 C6 CHK_FUNC6 C9 1D D0 03 4C 65 C4 CHK_FUNC7 C9 1F D0 03 4C 36 C4 CHK_FUNC8 C9 13 D0 03 4C 67 C6 CHK_FUNC9 CMP #13H BNE CHK_FUNC10 JMP KEY_STEP C9 16 D0 03 4C 03 C4 CHK_FUNC10 CMP #16H BNE CHK_FUNC11 JMP KEY_INS C9 17 D0 04 4C 02 C4 60 CHK_FUNC11 CMP #17H BNE CHK_FUNC12 JMP KEY_DEL RTS CMP #18H BNE CHK_FUNC5 JMP KEY_PC CMP #1BH BNE CHK_FUNC6 JMP KEY_REG CMP #12H BNE CHK_FUNC7 JMP KEY_GO CMP #1DH BNE CHK_FUNC8 JMP KEY_REL CMP #1FH BNE CHK_FUNC9 JMP KEY_DOWNLOAD_HEX CHK_FUNC12 60 RTS Page 13 of 28 MONITOR.LST 0989 0990 0991 0992 0993 0994 0995 0996 0997 0998 0999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 C401 C401 C401 C402 C402 C402 C403 C403 C403 C403 C403 C403 C405 C407 C409 C40B C40D C40D C410 C411 C411 C413 C415 C417 C419 C419 C41A C41C C41E C420 C420 C420 C420 C420 C421 C421 C421 C421 C421 C421 C421 C421 C421 C421 C423 C425 C425 C427 C429 C42C C42E C430 C432 C434 C435 C435 C436 C436 C436 C436 C436 C436 C438 C43A C43C C43E C440 C442 C444 C446 C448 C44A C44C C44E C450 C450 8/10/2015 6:21 PM 60 ;---------------------------------------------------------------NO_RESPONSE RTS 60 KEY_DEL RTS ;-----------------------------------------------------------------; insert byte to current display+1 ; shift down 1kB, 256 bytes. A5 C9 F0 C9 F0 94 01 08 02 04 20 01 C4 60 A5 85 A5 85 96 86 97 87 KEY_INS CMP #2 BEQ KEY_INS1 JSR NO_RESPONSE RTS KEY_INS1 LDA DISPLAY STA DE LDA DISPLAY+1 STA DE+1 18 A5 87 69 28 85 87 CLC 60 RTS A9 07 85 94 A9 85 20 A9 85 A9 85 60 00 95 81 C4 AE 8C 02 8D 60 LDA STATE CMP #1 BEQ KEY_INS1 LDA DE+1 ADC #40 ; DE=DE+$400 STA DE+1 ;-------------------------------------------------------------------KEY_SEND_HEX LDA #7 STA STATE ; STATE = 7 FOR SENDING HEX FILE STA JSR LDA STA LDA STA RTS LDA #0 ZERO_FLAG STILL_ADDRESS #0AEH BUFFER #2 BUFFER+1 RTS ;------------------------------------------------------------KEY_DOWNLOAD_HEX A9 85 A9 85 A9 85 A9 85 A9 85 A9 85 85 B3 91 85 91 A3 90 3F 8F B3 8E 00 8D 8C LDA STA LDA STA LDA STA LDA STA LDA STA LDA STA STA #0B3H ; PRINT LOAD BUFFER+5 #85H BUFFER+5 #0A3H BUFFER+4 #3FH BUFFER+3 #0B3H BUFFER+2 #0 BUFFER+1 BUFFER ; JSR NEW_LINE Page 14 of 28 MONITOR.LST 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 C450 C450 C450 C452 C454 C455 C455 C457 C45A C45A C45A C45D C45D C45F C461 C464 C464 C465 C465 C465 C465 C467 C469 C469 C46B C46D C470 C472 C474 C476 C478 C479 C479 C479 C479 C47B C47D C47D C47F C481 C481 C481 C484 C484 C486 C488 C48A C48A C48C C48E C490 C490 C492 C494 C496 C496 C498 C49A C49C C49C C49E C4A0 C4A2 C4A2 C4A4 C4A6 C4A8 C4A8 C4A9 C4A9 C4AB C4AD C4AD C4AF C4B1 C4B1 8/10/2015 6:21 PM A9 0A 85 94 60 A9 55 8D 00 80 ; JSR NEW_LINE ; JSR NEW_LINE LDA #10 STA STATE RTS GO_STATE10 LDA #55H STA GPIO1 20 5F C1 JSR GET_RECORD A9 02 85 94 20 B1 C4 LDA #2 STA STATE JSR STILL_DATA 60 RTS A9 05 85 94 A9 85 20 A9 85 A9 85 60 00 95 81 C4 AE 8C 02 8D A9 01 85 94 A9 00 85 95 ; GET INTEL HEX FILE ;----------------------------------------------------------KEY_REL LDA #5 STA STATE ; STATE = 5 FOR RELATIVE BYTE CALCULATION STA JSR LDA STA LDA STA RTS LDA #0 ZERO_FLAG STILL_ADDRESS #0AEH BUFFER #2 BUFFER+1 ;--------------------------------------------------------KEY_ADDR LDA #1 STA STATE ; STATE =1 FOR ADDRESS MODE LDA #0 STA ZERO_FLAG STILL_ADDRESS 20 D9 C4 JSR READ_MEMORY A5 91 09 40 85 91 LDA BUFFER+5 ORA #40H STA BUFFER+5 A5 90 09 40 85 90 LDA BUFFER+4 ORA #40H STA BUFFER+4 A5 8F 09 40 85 8F LDA BUFFER+3 ORA #40H STA BUFFER+3 A5 8E 09 40 85 8E LDA BUFFER+2 ORA #40H STA BUFFER+2 A5 8D 29 BF 85 8D LDA BUFFER+1 AND #~40H STA BUFFER+1 A5 8C 29 BF 85 8C LDA BUFFER AND #~40H STA BUFFER 60 A9 02 85 94 A9 00 85 95 20 D9 C4 RTS ;--------------------------------------------------------KEY_DATA LDA #2 STA STATE ; STATE =2 FOR DATA MODE LDA #0 STA ZERO_FLAG STILL_DATA JSR READ_MEMORY Page 15 of 28 MONITOR.LST 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 C4B4 C4B4 C4B6 C4B8 C4BA C4BA C4BC C4BE C4C0 C4C0 C4C2 C4C4 C4C6 C4C6 C4C8 C4CA C4CC C4CC C4CE C4D0 C4D2 C4D2 C4D4 C4D6 C4D8 C4D8 C4D9 C4D9 C4D9 C4D9 C4D9 C4D9 C4D9 C4DB C4DD C4DF C4E1 C4E4 C4E6 C4E8 C4E8 C4E8 C4E8 C4EB C4EC C4EC C4EC C4EF C4F1 C4F3 C4F5 C4F7 C4F8 C4F8 C4FB C4FD C4FF C501 C503 C504 C504 C504 C504 C507 C509 C50B C50D C50F C510 C510 C510 C510 C513 C515 C517 C519 8/10/2015 6:21 PM A5 91 29 BF 85 91 LDA BUFFER+5 AND #~40H STA BUFFER+5 A5 90 29 BF 85 90 LDA BUFFER+4 AND #~40H STA BUFFER+4 A5 8F 29 BF 85 8F LDA BUFFER+3 AND #~40H STA BUFFER+3 A5 8E 29 BF 85 8E LDA BUFFER+2 AND #~40H STA BUFFER+2 A5 8D 09 40 85 8D LDA BUFFER+1 ORA #40H STA BUFFER+1 A5 8C 09 40 85 8C LDA BUFFER ORA #40H STA BUFFER 60 RTS ; READ MEMORY READ_MEMORY A5 85 A5 85 20 A0 B1 96 84 97 85 4B C3 00 84 LDA DISPLAY HL DISPLAY+1 HL+1 ADDRESS_DISPLAY LDY #0 LDA (HL),Y STA LDA STA JSR ;STA GPIO1 20 3D C3 60 JSR DATA_DISPLAY RTS ;------------------------------------------------------------ 20 A9 85 A9 85 60 1C C5 AE 8C 02 8D HEX_SEND_FILE JSR HEX_ADDR LDA #0AEH STA BUFFER LDA #2 STA BUFFER+1 RTS 20 A9 85 A9 85 60 1C C5 8F 8C 02 8D HEX_SEND_FILE2 JSR HEX_ADDR LDA #08FH STA BUFFER LDA #2 STA BUFFER+1 RTS ;------------------------------------------------------------ 20 A9 85 A9 85 60 1C C5 AE 8C 02 8D HEX_REL JSR HEX_ADDR LDA #0AEH STA BUFFER LDA #2 STA BUFFER+1 RTS 20 A9 85 A9 85 1C C5 B3 8C 02 8D HEX_REL6 JSR HEX_ADDR LDA #0B3H STA BUFFER LDA #2 STA BUFFER+1 Page 16 of 28 MONITOR.LST 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 C51B C51C C51C C51C C51C C51C C51E C520 C522 C522 C524 C526 C528 C52A C52C C52C C52D C52F C531 C531 C532 C534 C536 C536 C537 C539 C53B C53B C53C C53E C540 C540 C542 C544 C546 C546 C546 C546 C549 C549 C54A C54A C54A C54A C54C C54E C550 C550 C552 C554 C554 C556 C558 C55A C55A C55C C55E C55F C560 C561 C562 C564 C566 C566 C566 C569 C56A C56A C56A C56A C56A C56C C56E C570 C570 C572 8/10/2015 6:21 PM 60 RTS ;------------------- HEX KEY FOR ADDRESS ------------------- A5 95 C9 00 D0 0A A9 85 A9 85 85 01 95 00 96 97 HEX_ADDR LDA ZERO_FLAG CMP #0 BNE SHIFT_ADDRESS LDA #1 STA ZERO_FLAG LDA #0 STA DISPLAY STA DISPLAY+1 18 26 96 26 97 SHIFT_ADDRESS CLC ROL DISPLAY ROL DISPLAY+1 18 26 96 26 97 CLC ROL DISPLAY ROL DISPLAY+1 18 26 96 26 97 CLC 18 26 96 26 97 CLC A5 96 05 83 85 96 LDA DISPLAY ORA REG_C STA DISPLAY ROL DISPLAY ROL DISPLAY+1 ROL DISPLAY ROL DISPLAY+1 ; JSR READ_MEMORY 20 81 C4 JSR STILL_ADDRESS 60 RTS ;------------------------- HEX KEY FOR DATA MODE -------------------------- A5 95 C9 00 D0 0A HEX_DATA LDA ZERO_FLAG CMP #0 BNE SHIFT_DATA A9 01 85 95 LDA #1 STA ZERO_FLAG A9 00 A0 00 91 96 LDA #0 LDY #0 STA (DISPLAY),Y A0 B1 0A 0A 0A 0A 05 91 00 96 83 96 20 B1 C4 60 SHIFT_DATA ASL ASL ASL ASL ORA STA LDY #0 LDA (DISPLAY),Y A A A A REG_C (DISPLAY),Y ; JSR READ_MEMORY JSR STILL_DATA RTS ; INCREMENT CURRENT ADDRESS BY ONE ; A5 94 C9 05 F0 1D C9 07 F0 35 KEY_INC LDA STATE CMP #5 BEQ REL_KEY_PRESSED CMP #7 BEQ SEND_INC1 Page 17 of 28 MONITOR.LST 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 C574 C574 C576 C578 C578 C57A C57C C57C C57C C57D C57F C581 C583 C585 C587 C589 C589 C58C C58D C58D C58D C58D C58D C58D C58F C591 C593 C595 C595 C597 C599 C59B C59D C59D C5A0 C5A2 C5A4 C5A6 C5A8 C5A9 C5A9 C5A9 C5A9 C5A9 C5AB C5AD C5AF C5B1 C5B1 C5B3 C5B5 C5B7 C5B9 C5B9 C5BC C5BE C5C0 C5C2 C5C4 C5C5 C5C5 C5C5 C5C5 C5C5 C5C5 C5C5 C5C5 C5C5 C5C5 C5C5 C5C7 C5C9 C5C9 C5CB C5CD C5CD 8/10/2015 6:21 PM A9 02 85 94 A9 00 85 95 18 A5 69 85 A5 69 85 96 01 96 97 00 97 20 B1 C4 60 LDA #2 STA STATE ; STATE =2 FOR DATA MODE LDA #0 STA ZERO_FLAG CLC LDA DISPLAY ADC STA LDA ADC STA #1 DISPLAY DISPLAY+1 #0 DISPLAY+1 ; JSR READ_MEMORY JSR STILL_DATA RTS REL_KEY_PRESSED ; Save start address A5 85 A5 85 96 A0 97 A1 LDA STA LDA STA A9 85 A9 85 06 94 00 95 LDA #6 STA STATE LDA #0 STA ZERO_FLAG 20 A9 85 A9 85 60 81 C4 B3 8C 02 8D JSR LDA STA LDA STA RTS SEND_INC1 DISPLAY START_ADDRESS DISPLAY+1 START_ADDRESS+1 STILL_ADDRESS #0B3H BUFFER #2 BUFFER+1 ; Save start address A5 85 A5 85 96 A0 97 A1 LDA STA LDA STA DISPLAY START_ADDRESS DISPLAY+1 START_ADDRESS+1 A9 85 A9 85 08 94 00 95 LDA #8 STA STATE LDA #0 STA ZERO_FLAG 20 A9 85 A9 85 60 81 C4 8F 8C 02 8D JSR LDA STA LDA STA RTS STILL_ADDRESS #08FH BUFFER #2 BUFFER+1 ; DECREMENT CURRENT ADDRESS BY ONE ; A9 02 85 94 A9 00 85 95 KEY_DEC LDA #2 STA STATE ; STATE =2 FOR DATA MODE LDA #0 STA ZERO_FLAG Page 18 of 28 MONITOR.LST 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 C5CD C5CE C5D0 C5D2 C5D4 C5D6 C5D8 C5DA C5DA C5DD C5DE C5DE C5DE C5DE C5E0 C5E2 C5E2 C5E4 C5E6 C5E6 C5E8 C5EA C5EC C5EE C5EE C5F1 C5F2 C5F2 C5F2 C5F2 C5F2 C5F4 C5F6 C5F6 C5F8 C5FA C5FC C5FE C600 C602 C604 C606 C608 C60A C60C C60C C60D C60D C60D C60D C60D C60F C611 C613 C615 C615 C615 C617 C619 C61B C61D C61D C61E C620 C622 C624 C624 C626 C628 C62A C62A C62A C62A C62C C62E C62E 8/10/2015 6:21 PM 38 A5 E9 85 A5 E9 85 SEC LDA DISPLAY 96 01 96 97 00 97 SBC STA LDA SBC STA #1 DISPLAY DISPLAY+1 #0 DISPLAY+1 ; JSR READ_MEMORY JSR STILL_DATA RTS 20 B1 C4 60 ; KEY PC, SET CURRENT USER ADDRESS A9 02 85 94 KEY_PC LDA #2 STA STATE A9 00 85 95 LDA #0 STA ZERO_FLAG A5 85 A5 85 LDA STA LDA STA 98 96 99 97 ; STATE =2 FOR DATA MODE PC_USER DISPLAY PC_USER+1 DISPLAY+1 ; JSR READ_MEMORY JSR STILL_DATA RTS 20 B1 C4 60 ; KEY REGSITER ; SET STATE TO 3 FOR REGISTER INPUT WITH HEX KEY A9 03 85 94 A9 85 A9 85 A9 85 A9 85 A9 85 85 KEY_REG 03 91 8F 90 BE 8F 02 8E 00 8D 8C LDA STA LDA STA LDA STA LDA STA LDA STA STA 60 LDA #3 STA STATE ; STATE = 3 FOR REGISTER DISPLAY #3 BUFFER+5 #8FH BUFFER+4 #0BEH BUFFER+3 #2 BUFFER+2 #0 BUFFER+1 BUFFER RTS ;--------------------------------------------------------------------------GO_STATE8 A5 85 A5 85 96 A2 97 A3 LDA STA LDA STA DISPLAY DESTINATION DISPLAY+1 DESTINATION+1 A5 85 A5 85 A0 84 A1 85 ; NOW COMPUTE NUMBER OF BYTE = DESTINATION - START_ADDRESS LDA START_ADDRESS STA HL LDA START_ADDRESS+1 STA HL+1 38 A5 A2 E5 84 85 A4 SEC LDA DESTINATION SBC HL STA OFFSET_BYTE A5 A3 E5 85 85 A5 LDA DESTINATION+1 SBC HL+1 STA OFFSET_BYTE+1 ; DESTINATION IS NOW ENDING ADDRESS ; OFFSET = NUMBER OF BYTE ; DEVIDE NUMBER OF BYTE WITH 16 TO GET NUMBER OF RECORD TO BE SENT 46 A5 66 A4 LSR OFFSET_BYTE+1 ROR OFFSET_BYTE 46 A5 LSR OFFSET_BYTE+1 Page 19 of 28 MONITOR.LST 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 C630 C632 C632 C634 C636 C636 C638 C63A C63A C63C C63F C63F C640 C640 C640 C643 C643 C643 C643 C643 C645 C647 C649 C649 C64B C64D C64D C64F C651 C651 C652 C654 C654 C654 C654 C656 C657 C657 C659 C65A C65C C65D C65F C660 C662 C664 C666 C667 C667 C667 C667 C667 C668 C66A C66A C66A C66A C66C C66D C66D C66D C66D C66F C671 C673 C675 C675 C675 C675 C677 C678 C67A C67B C67D C67E C680 8/10/2015 6:21 PM 66 A4 ROR OFFSET_BYTE 46 A5 66 A4 LSR OFFSET_BYTE+1 ROR OFFSET_BYTE 46 A5 66 A4 LSR OFFSET_BYTE+1 ROR OFFSET_BYTE A5 A4 8D 00 80 LDA OFFSET_BYTE ; CHECK RESULT STA GPIO1 60 RTS 4C 55 C4 SHORT_GO_STATE10 JMP GO_STATE10 ; KEY GO WRITE USER REGISTERS TO STACK AND USE RTI TO JUMP TO USER PROGRAM ; A5 94 C9 06 F0 46 KEY_GO LDA STATE CMP #6 BEQ GO_STATE6 C9 08 F0 C0 CMP #8 BEQ GO_STATE8 C9 0A F0 EF CMP #10 BEQ SHORT_GO_STATE10 BA 86 9F TSX STX SAVE_SP ; SAVE SYSTEM STACK ; NOW SWITCH TO USER STACK A6 9D 9A A5 48 A5 48 A5 48 A6 A4 A5 40 97 96 9E 9B 9C 9A LDX USER_S TXS LDA DISPLAY+1 PHA LDA DISPLAY PHA LDA USER_P PHA LDX USER_X LDY USER_Y LDA USER_A RTI ;---------------------- SINGLE STEP -----------------------KEY_STEP BA 86 9F TSX STX SAVE_SP ; SAVE SYSTEM STACK ; NOW SWITCH TO USER STACK A6 9D 9A LDX USER_S TXS ; LOAD CURRENT PC TO DISPLAY A5 85 A5 85 98 96 99 97 A5 48 A5 48 A5 48 A6 A4 97 96 9E 9B 9C LDA PC_USER STA DISPLAY LDA PC_USER+1 STA DISPLAY+1 LDA DISPLAY+1 PHA LDA PHA LDA PHA LDX LDY DISPLAY USER_P USER_X USER_Y Page 20 of 28 MONITOR.LST 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 C682 C682 C684 C687 C687 C688 C689 C68A C68B C68C C68E C68F C68F C68F C68F C68F C68F C68F C68F C68F C68F C68F C691 C693 C695 C697 C697 C697 C697 C697 C697 C699 C69B C69D C69F C6A2 C6A5 C6A5 C6A6 C6A8 C6AA C6AC C6AC C6AE C6B0 C6B2 C6B2 C6B2 C6B2 C6B2 C6B2 C6B2 C6B4 C6B6 C6B8 C6B8 C6B8 C6B8 C6BA C6BC C6BE C6BE C6C1 C6C1 C6C1 C6C3 C6C5 C6C5 C6C5 C6C5 C6C7 C6C9 C6CB C6CD C6D0 C6D0 8/10/2015 6:21 PM A9 FF 8D 02 80 LDA #$FF STA PORT1 EA EA EA EA EA A5 9A 40 NOP NOP NOP NOP NOP LDA USER_A RTI ; BREAK MUST BE LOGIC HIGH TO ENABLE IT ; ; ; USER INSTRUCTION IS 8TH FETCHING, IT WILL JUMP TO NMI SERVICE ; KEY GO WITH RELATIVE CALCULATION ; FIND OFFSET BYTE GO_STATE6 A5 85 A5 85 96 A2 97 A3 LDA DISPLAY STA DESTINATION LDA DISPLAY+1 STA DESTINATION+1 ; NOW COMPUTE OFFSET_BYTE = DESTINATION - START_ADDRESS ; THE REAL PC WILL BE NEXT INTSRUCTION ADDRESS (+2 FROM BRANCH INSTRUCTION A5 85 A5 85 20 20 A0 84 A1 85 C5 C0 C5 C0 STA LDA STA JSR JSR LDA START_ADDRESS HL START_ADDRESS+1 HL+1 INC_HL INC_HL 38 A5 A2 E5 84 85 A4 SEC LDA DESTINATION SBC HL STA OFFSET_BYTE A5 A3 E5 85 85 A5 LDA DESTINATION+1 SBC HL+1 STA OFFSET_BYTE+1 ; ; ; ; A5 A4 29 80 F0 09 CHECK IF THE OFFSET BYTE WAS BETWEEN -128 (FF80) TO +127 (007F) IF BIT 7 OF THE OFFSET BYTE IS 0, THE HIGH BYTE MUST BE ZERO IF BIT 7 OF THE OFFSET BYTE IS 1, THE HIGH BYTE MUST BE FF OTHERWISE, THE OFFSET BYTE WAS OUT OF RANGE, SHOW ERROR THEN LDA OFFSET_BYTE AND #80H BEQ CHK_OFFSET_HIGH ; CHECK HIGH BYTE MUST BE FF (-1) A5 A5 C9 FF D0 28 LDA OFFSET_BYTE+1 CMP #0FFH BNE OUT_OFF_RANGE 4C C5 C6 JMP IN_RANGE A5 A5 D0 21 CHK_OFFSET_HIGH LDA OFFSET_BYTE+1 BNE OUT_OFF_RANGE ; STORE OFFSET TO THE 2ND BYTE OF BRANCH INSTRUCTION A5 85 A5 85 20 A0 84 A1 85 C5 C0 A5 A4 IN_RANGE LDA START_ADDRESS STA HL LDA START_ADDRESS+1 STA HL+1 JSR INC_HL LDA OFFSET_BYTE Page 21 of 28 MONITOR.LST 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 C6D2 C6D4 C6D6 C6D6 C6D8 C6DA C6DC C6DE C6DE C6DE C6E1 C6E1 C6E3 C6E5 C6E6 C6E6 C6E6 C6E6 C6E8 C6EA C6EC C6EE C6F0 C6F2 C6F4 C6F6 C6F8 C6FA C6FC C6FC C6FE C700 C700 C701 C701 C701 C701 C701 C701 C701 C701 C701 C701 C701 C701 C701 C703 C703 C703 C705 C708 C708 C708 C708 C709 C70B C70B C70C C70E C710 C711 C713 C715 C717 C719 C719 C71A C71C C71C C71F C71F C71F C71F C721 C722 C722 8/10/2015 6:21 PM A0 00 91 84 LDY #0 STA (HL),Y A5 85 A5 85 LDA STA LDA STA 84 96 85 97 HL DISPLAY HL+1 DISPLAY+1 20 B1 C4 JSR STILL_DATA A9 02 85 94 60 LDA #2 STA STATE RTS ; DISPLAY LOCATION OF OFFSET BYTE OUT_OFF_RANGE A9 85 A9 85 A9 85 A9 85 A9 85 85 02 91 8F 90 03 8F 03 8E 00 8D 8C STA LDA STA LDA STA LDA STA LDA STA STA LDA #2 BUFFER+5 #8FH BUFFER+4 #3 BUFFER+3 #3 BUFFER+2 #0 BUFFER+1 BUFFER A9 02 85 94 LDA #2 STA STATE 60 RTS ; NMI SERVICE ROUTINE ; SAVE CPU REGISTERS TO USER REGISTERS FOR PROGRAM DEBUGGING NMI_SERVICE 85 9A A9 BF 8D 02 80 STA USER_A ; STA GPIO1 LDA #$BF STA PORT1 ; 8-BIT DISPLAY WILL SHOW CONTENT OF ACCUMULATOR ; TURN OFF BRK SIGNAL ; STILL WITH USER STACK 68 85 9E PLA STA USER_P 68 85 85 68 85 85 84 86 PLA STA STA PLA STA STA STY STX 96 98 97 99 9C 9B DISPLAY PC_USER DISPLAY+1 PC_USER+1 USER_Y USER_X BA 86 9D TSX STX USER_S 20 79 C4 JSR KEY_ADDR ; DISPLAY LOCATION THAT BREAKED ; RESTORE SYSTEM STACK A6 9F 9A LDX SAVE_SP TXS 60 RTS Page 22 of 28 MONITOR.LST 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 C723 C723 C723 C723 C725 C727 C729 C729 C72B C72B C72E C730 C732 C734 C736 C738 C73A C73C C73D C73D C73D C73F C741 C741 C743 C743 C743 C746 C748 C74A C74C C74E C750 C752 C754 C755 C755 C757 C759 C759 C75B C75B C75B C75E C760 C762 C764 C766 C768 C76A C76C C76D C76D C76D C76F C771 C771 C773 C773 C773 C776 C778 C77A C77C C77E C780 C782 C784 C785 C785 C787 C789 C789 C78B C78D C78F 8/10/2015 6:21 PM ; DISPLAY USER REGSITERS A5 83 C9 00 D0 14 HEX_REG A5 9A LDA USER_A ; STA GPIO1 JSR DATA_DISPLAY LDA #82H STA BUFFER+2 LDA #3FH ; REGISTER A STA BUFFER+3 LDA #0 STA BUFFER+4 STA BUFFER+5 RTS 20 A9 85 A9 85 A9 85 85 60 3D C3 82 8E 3F 8F 00 90 91 LDA REG_C CMP #0 BNE CHK_REG1 CHK_REG1 C9 01 D0 14 A5 9B 20 A9 85 A9 85 A9 85 85 60 3D C3 82 8E 07 8F 00 90 91 CMP #1 BNE CHK_REG2 LDA USER_X ; STA GPIO1 JSR LDA STA LDA STA LDA STA STA RTS DATA_DISPLAY #82H BUFFER+2 #7 ; REGISTER X BUFFER+3 #0 BUFFER+4 BUFFER+5 C9 02 D0 14 CHK_REG2 CMP #2 BNE CHK_REG3 A5 9C LDA USER_Y ; STA GPIO1 20 A9 85 A9 85 A9 85 85 60 3D C3 82 8E B6 8F 00 90 91 JSR LDA STA LDA STA LDA STA STA RTS DATA_DISPLAY #82H BUFFER+2 #0B6H ; REGISTER Y BUFFER+3 #0 BUFFER+4 BUFFER+5 C9 03 D0 14 CHK_REG3 CMP #3 BNE CHK_REG4 A5 9D LDA USER_S ; STA GPIO1 20 A9 85 A9 85 A9 85 85 60 3D C3 82 8E AE 8F 00 90 91 C9 05 D0 42 A9 00 85 84 85 85 JSR LDA STA LDA STA LDA STA STA RTS DATA_DISPLAY #82H BUFFER+2 #0AEH ; REGISTER S BUFFER+3 #0 BUFFER+4 BUFFER+5 CHK_REG4 CMP #5 BNE CHK_REG5 LDA #0 STA HL STA HL+1 ; RESET HL TO 0000 Page 23 of 28 MONITOR.LST 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 C78F C791 C791 C793 C795 C797 C799 C79B C79B C79D C79F C7A1 C7A1 C7A3 C7A5 C7A7 C7A7 C7A9 C7AB C7AD C7AD C7AF C7B1 C7B3 C7B3 C7B5 C7B7 C7B9 C7B9 C7BB C7BD C7BF C7C2 C7C2 C7C4 C7C6 C7C8 C7CA C7CB C7CB C7CB C7CD C7CF C7CF C7D1 C7D3 C7D5 C7D5 C7D7 C7D7 C7D7 C7D9 C7DB C7DD C7DF C7E1 C7E1 C7E3 C7E5 C7E7 C7E9 C7EB C7ED C7ED C7EF C7F1 C7F3 C7F3 C7F5 C7F7 C7F9 C7F9 C7FB C7FD C7FF C7FF 8/10/2015 6:21 PM A5 9E 29 F0 A5 09 85 LDA USER_P ; STA GPIO1 AND #1 BEQ NEXT_BIT1 LDA HL ORA #1 STA HL 01 06 84 01 84 A5 9E 29 02 F0 06 NEXT_BIT1 LDA USER_P AND #2 BEQ NEXT_BIT2 A5 84 09 10 85 84 A5 9E 29 04 F0 06 LDA HL ORA #10H STA HL NEXT_BIT2 LDA USER_P AND #4 BEQ NEXT_BIT3 A5 85 09 01 85 85 LDA HL+1 ORA #1 STA HL+1 A5 9E 29 08 F0 06 NEXT_BIT3 LDA USER_P AND #8 BEQ OK1 A5 09 85 20 85 10 85 4B C3 LDA HL+1 ORA #10H STA HL+1 OK1 JSR ADDRESS_DISPLAY A9 85 A9 85 60 1F 8D 85 8C C9 04 D0 42 LDA STA LDA STA #1FH BUFFER+1 #085H BUFFER RTS CHK_REG5 A9 00 85 84 85 85 CMP #4 BNE CHK_REG6 LDA #0 STA HL STA HL+1 A5 9E ; LDA USER_P STA GPIO1 29 F0 A5 09 85 10 06 84 01 84 A5 29 F0 A5 09 85 9E 20 06 84 10 84 NEXT_BIT4 LDA USER_P AND #20H BEQ NEXT_BIT5 LDA HL ORA #10H STA HL A5 9E 29 40 F0 06 NEXT_BIT5 LDA USER_P AND #40H BEQ NEXT_BIT6 A5 85 09 01 85 85 A5 9E 29 80 F0 06 A5 85 ; RESET HL TO 0000 AND BEQ LDA ORA STA #10H NEXT_BIT4 HL #1 HL LDA HL+1 ORA #1 STA HL+1 NEXT_BIT6 LDA USER_P AND #80H BEQ OK2 LDA HL+1 Page 24 of 28 MONITOR.LST 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 C801 C803 C805 C805 C808 C808 C80A C80C C80E C810 C811 C811 C813 C815 C815 C815 C815 C816 C818 C818 C818 C819 C81B C81D C81D C820 C820 C822 C822 C823 C825 C828 C828 C82A C82C C82E C830 C831 C831 C831 C832 C832 C832 C832 C832 C835 C837 C839 C839 C83B C83D C840 C843 C845 C848 C84B C84B C84C C84E C84E C84F C84F C851 C852 C854 C855 C855 C855 C855 C855 C855 C855 C857 C859 C859 C85B 8/10/2015 6:21 PM 09 10 85 85 ORA #10H STA HL+1 20 4B C3 A9 85 A9 85 60 1F 8D 37 8C OK2 LDA STA LDA STA C9 10 B0 1C JSR ADDRESS_DISPLAY #1FH BUFFER+1 #37H BUFFER RTS CHK_REG6 CMP #10H BCS NOT_HEX ; NOW DISPLAY PAGE ZERO BYTE FROM 0 TO 9 38 E9 06 SEC SBC #6 ; NOW A IS LOCATION IS PAGE ZERO 0-9 TAX LDA 0,X STX SAVE_X AA B5 00 86 A8 20 3D C3 JSR DATA_DISPLAY A6 A8 LDX SAVE_X 8A 85 85 20 4B C3 TXA STA HL+1 JSR ADDRESS_DISPLAY A9 85 A9 85 60 LDA STA LDA STA RTS 82 8F 00 8E #82H BUFFER+3 #0 BUFFER+2 NOT_HEX 60 RTS ; PRODUCE BEEP WHEN KEY PRESSED ; CALIBRATED TO 523Hz AD 01 80 29 40 F0 15 BEEP A2 A9 8D 20 A9 8D 20 LDX #40H BEEP2 LDA #3FH STA PORT1 JSR BEEP_DELAY LDA #0BFH STA PORT1 JSR BEEP_DELAY 40 3F 02 4F BF 02 4F CA D0 ED 80 C8 80 C8 LDA PORT0 AND #40H BEQ NO_BEEP ; CHECK IF REPEAT KEY IS PRESSED, THEN NO BEEP DEX BNE BEEP2 60 NO_BEEP RTS A0 BB 88 D0 FD 60 BEEP_DELAY LDY #0BBH BEEP_LOOP DEY BNE BEEP_LOOP RTS ; ; DISPLAY COLD BOOT MESSAGE ; COLD_MESSAGE A9 0A 85 81 LDA #10 A9 08 85 82 LDA #8 STA REG_B STA REG_D Page 25 of 28 MONITOR.LST 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 C85D C85D C85F C85F C85F C862 C862 C864 C866 C866 C867 C867 C869 C86B C86C C86C C86C C86C C86C C86C C86C C86C C86C C86F C872 C872 C872 C872 C872 C874 C876 C878 C87A C87A C87A C87A C87C C87E C880 C882 C884 C886 C888 C88A C88A C88A C88A C88A C88A C88C C88E C890 C890 C892 C894 C896 C896 C898 C899 C89B C89D C89D C89E C89F C89F C8A1 C8A3 C8A5 C8A5 C8A7 C8A9 C8AB C8AD C8AF C8B1 C8B1 8/10/2015 6:21 PM A2 07 20 66 C2 LDX #7 DISPLAY2 JSR SCAN2 C6 81 D0 F9 DEC REG_D BNE DISPLAY2 CA DEX C6 82 D0 F4 60 DEC REG_B BNE DISPLAY2 RTS ; NMI and IRQ are called via RAM-vector. This enables the programmer ; to insert his own routines. 6C FA 00 6C FE 00 NMI IRQ JMP JMP ($FA) ($FE) ;------------------------------------------------------------A9 85 85 85 00 8C 8D 92 MAIN LDA #0 STA BUFFER STA BUFFER+1 STA INVALID ; CLEAR INVALID FLAG ; INSERT 6502 TEXT A9 85 A9 85 A9 85 A9 85 AF 91 AE 90 BD 8F 9B 8E LDA #0AFH STA BUFFER+5 LDA #0AEH STA BUFFER+4 LDA #0BDH STA BUFFER+3 LDA #9BH STA BUFFER+2 ; STORE VECTOR INTERRUPT A9 01 85 FA 85 FE LDA #NMI_SERVICE&0FFH STA $FA STA $FE A9 C7 85 FB 85 FF LDA #(NMI_SERVICE>>8) STA $FB STA $FF A2 FF 9A A9 7F 85 9D LDX #$FF TXS ; SET SYSTEM STACK TO 1FFH LDA #$7F ; AND USER STACK TO 17FH STA USER_S D8 78 CLD SEI A9 00 85 94 85 95 LDA #0 STA STATE ; INITIAL STATE STA ZERO_FLAG A9 85 85 A9 85 85 STA STA LDA STA STA 00 96 98 02 97 99 ; NMI MUST BE SET BEFORE USING SINGLE STEP ; DISABLE IRQ LDA #0 DISPLAY PC_USER #02H DISPLAY+1 PC_USER+1 Page 26 of 28 MONITOR.LST 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 C8B1 C8B3 C8B5 C8B7 C8B9 C8B9 C8B9 C8B9 C8B9 C8BB C8BD C8BD C8BD C8BF C8C1 C8C3 C8C3 C8C5 C8C7 C8C7 C8C7 C8C9 C8CC C8CC C8CF C8D2 C8D2 C8D2 C8D4 C8D7 C8D7 C8DA C8DD C8E0 C8E3 C8E3 C8E3 C8E3 C8E3 C8E3 C8E3 C8E3 C8E3 C8E4 C8E5 C8E6 C8E7 C8E8 C8E9 C8EA C8EB C8EC C8ED C8EE C8EF C8EF C8EF C8F0 C8F1 C8F2 C8F3 C8F4 C8F5 C8F6 C8F7 C8F8 C8F9 C8FA C8FB C8FC C8FD C8FE C8FF C8FF C8FF C8FF 8/10/2015 6:21 PM A5 85 A5 85 96 84 97 85 LDA DISPLAY STA HL LDA DISPLAY+1 STA HL+1 A0 00 B1 84 ;JSR ADDRESS_DISPLAY LDY #0 LDA (HL),Y ;JSR DATA_DISPLAY A5 A6 C9 99 F0 0F LDA COLD CMP #99H BEQ WARM_BOOT A9 99 85 A6 LDA #99H STA COLD A9 FF 8D 00 80 LDA #$FF STA GPIO1 ; TEST GPIO1 20 55 C8 20 32 C8 JSR COLD_MESSAGE JSR BEEP A9 00 8D 00 80 WARM_BOOT LDA #0 STA GPIO1 20 20 20 4C LOOP3 JSR SCANKEY JSR KEYEXE JSR BEEP JMP LOOP3 ED 66 32 D7 C2 C3 C8 C8 00 00 9B BD AE AF 00 00 00 00 00 00 ;-------------------------------------------------------------START_MSG .BYTE 0 .BYTE 0 .BYTE 9BH .BYTE 0BDH .BYTE 0AEH .BYTE 0AFH .BYTE 0 .BYTE 0 .BYTE 0 .BYTE 0 .BYTE 0 .BYTE 0 BD 30 9B BA 36 AE AF 38 BF BE 3F A7 8D B3 8F 0F SEGTAB .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE 030H 09BH 0BAH 036H 0AEH 0AFH 038H 0BFH 0BEH 03FH 0A7H 08DH 0B3H 08FH 00FH 0BDH ;'1' ;'2' ;'3' ;'4' ;'5' ;'6' ;'7' ;'8' ;'9' ;'A' ;'B' ;'C' ;'D' ;'E' ;'F' ;'0' ; Key-posistion-code to key-internal-code conversion table. Page 27 of 28 MONITOR.LST 8/10/2015 6:21 PM 2053 C8FF 2054 C8FF KEYTAB: 2055 C8FF 03 K0 .BYTE 03H ;HEX_3 2056 C900 07 K1 .BYTE 07H ;HEX_7 2057 C901 0B K2 .BYTE 0BH ;HEX_B 2058 C902 0F K3 .BYTE 0FH ;HEX_F 2059 C903 20 K4 .BYTE 20H ;NOT USED 2060 C904 21 K5 .BYTE 21H ;NOT USED 2061 C905 02 K6 .BYTE 02H ;HEX_2 2062 C906 06 K7 .BYTE 06H ;HEX_6 2063 C907 0A K8 .BYTE 0AH ;HEX_A 2064 C908 0E K9 .BYTE 0EH ;HEX_E 2065 C909 22 K0A .BYTE 22H ;NOT USED 2066 C90A 23 K0B .BYTE 23H ;NOT USED 2067 C90B 01 K0C .BYTE 01H ;HEX_1 2068 C90C 05 K0D .BYTE 05H ;HEX_5 2069 C90D 09 K0E .BYTE 09H ;HEX_9 2070 C90E 0D K0F .BYTE 0DH ;HEX_D 2071 C90F 13 K10 .BYTE 13H ;STEP 2072 C910 1F K11 .BYTE 1FH ;TAPERD 2073 C911 00 K12 .BYTE 00H ;HEX_0 2074 C912 04 K13 .BYTE 04H ;HEX_4 2075 C913 08 K14 .BYTE 08H ;HEX_8 2076 C914 0C K15 .BYTE 0CH ;HEX_C 2077 C915 12 K16 .BYTE 12H ;GO 2078 C916 1E K17 .BYTE 1EH ;TAPEWR 2079 C917 1A K18 .BYTE 1AH ;CBR 2080 C918 18 K19 .BYTE 18H ;PC 2081 C919 1B K1A .BYTE 1BH ;REG 2082 C91A 19 K1B .BYTE 19H ;ADDR 2083 C91B 17 K1C .BYTE 17H ;DEL 2084 C91C 1D K1D .BYTE 1DH ;RELA 2085 C91D 15 K1E .BYTE 15H ;SBR 2086 C91E 11 K1F .BYTE 11H ;2087 C91F 14 K20 .BYTE 14H ;DATA 2088 C920 10 K21 .BYTE 10H ;+ 2089 C921 16 K22 .BYTE 16H ;INS 2090 C922 1C K23 .BYTE 1CH ;MOVE 2091 C923 2092 C923 ; PAGE FOR CONSTANT STRINGS AREA 2093 C923 2094 EF00 .ORG 0EF00H ; ROM MONITOR 2095 EF00 ; .ORG 06F00H ; RAM TEST 2096 EF00 2097 EF00 2098 EF00 ;TEXT1 .BYTE "6502 TRAINER KIT V1.0 ROM", 10, 13, 0 2099 EF00 363530322054TEXT1 .BYTE "6502 TRAINER KIT V1.0 RAM", 10, 13, 0 2099 EF06 5241494E4552204B49542056312E302052414D0A0D00 2100 EF1C 2101 EF1C 2102 EF1C 3E 3E 00 PROMPT .BYTE ">>", 0 2103 EF1F 2104 EF1F 2105 EF1F 2106 EF1F 2107 EF1F ; VECTOR NMI,RESET AND IRQ 2108 EF1F 2109 EF1F 2110 FFFA .ORG 0FFFAH 2111 FFFA 2112 FFFA 6C C8 .WORD NMI 2113 FFFC 00 C0 .WORD 0C000H ; RESET VECTOR 2114 FFFE 6F C8 .WORD IRQ ; IRQ VECTOR 2115 0000 2116 0000 2117 0000 2118 0000 2119 0000 .END 2120 0000 2121 0000 2122 0000 tasm: Number of errors = 0 Page 28 of 28 NOTE
