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Chapter 3: Functional Description
Performance Monitor for PCI Express
This monitor snoops on the AXI4-Stream PCIe 128-bit interface operating at 250 MHz and
provides the following measurements which are updated once every second:
•
Count of active beats upstream which include the TLP headers for various
transactions
•
Count of active beats downstream which include the TLP headers for various
transactions
•
Count of payload bytes for upstream memory write transactions – this includes buffer
write (in C2S) and buffer descriptor updates (for both S2C and C2S)
•
Count of payload bytes for downstream completion with data transactions – this
includes buffer fetch (in S2C) and buffer descriptor fetch (for both S2C and C2S)
These performance numbers measured are reflected in user space registers which software
can read periodically and display.
Table 3-1:
Monitor Ports for PCI Express
Port Name
Type
Description
reset
Input
Synchronous reset.
clk
Input
250 MHz clock.
Transmit Ports on the AXI4-Stream Interface
s_axis_tx_tdata[127:0]
Input
Data to be transmitted via PCIe link.
s_axis_tx_tlast
Input
End of frame indicator on transmit packets. Valid only along with assertion of
s_axis_tx_tvalid.
s_axis_tx_tvalid
Input
Source ready to provide transmit data. Indicates that the DMA is presenting
valid data on s_axis_tx_tdata.
s_axis_tx_tuser[3]
Input
Source discontinue on a transmit packet. Can be asserted any time starting on
the first cycle after SOF. s_axis_tx_tlast should be asserted along with
s_axis_tx_tuser[3] assertion.
s_axis_tx_tready
Input
Destination ready for transmit. Indicates that the core is ready to accept data on
s_axis_tx_tdata. The simultaneous assertion of s_axis_tx_tvalid and
s_axis_tx_tready marks the successful transfer of one data beat on
s_axis_tx_tdata.
Receive Ports on the AXI4-Stream Interface
m_axis_rx_tdata[127:0]
Input
Data received on the PCIe link. Valid only if m_axis_rx_tvalid is also asserted.
m_axis_rx_tlast
Input
End of frame indicator for received packet. Valid only if m_axis_rx_tvalid is
also asserted.
m_axis_rx_tvalid
Input
Source ready to provide receive data.Indicates that the core is presenting valid
data on m_axis_rx_tdata.
m_axis_rx_tready
Input
Destination ready for receive. Indicates that the DMA is ready to accept data
on m_axis_rx_tdata. The simultaneous assertion of m_axis_rx_tvalid and
m_axis_rx_tready marks the successful transfer of one data beat on
m_axis_rx_tdata.
Byte Count Ports
tx_byte_count[31:0]
38
Output
Raw transmit byte count.
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Kintex-7 FPGA Connectivity TRD
UG927 (v2.0) January 9, 2013