Download Hardware-Software Codesign of a Programmable

Appendix D
VHDL Code
if SFD_DETECTED = true then
write_enable <= ’1’;
else
write_enable <= ’0’; -- ANDing with SFD_DETECTED
end if;
word_counter := word_counter - 1;
else
write_enable <= ’0’;
-- after 1 ns;
end if;
if (word_counter=31 and byte_counter=3 and bit_counter=7
and chip_counter = 15 and SFD_DETECTED = true) then
SFD_DETECTED <= false; -- Detect another SFD
else
SFD_DETECTED <= true;
end if;
else
-- !if (DATA_PAYLOAD = true)
SFD_DETECTED <= false;
end if; -- if (DATA_PAYLOAD = true)
if SFD_DETECTED = false then
write_enable <= ’0’;
end if;
write_data <= std_logic_vector(current_word);
end if; -- rising clock edge
end process;
end behavioral;
The next file is the cpbuf.vhd file which has the buffer design in the WLRCV System.
--------------------------------------------------------------- Entity:
cpbuf
-- File:
cpbuf.vhd
-- Author:
Ambarish Sule
-- Description: A 32-byte "Round-Robin" buffer with separate
-Read and Write ports
-------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.iface.all;
entity cpbuf is
generic (
86