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FSF-AD8200A User Manual
This input can be left open and the 8-channel capture application included with the FSF-AD8200A
will operate correctly, but with a small frequency error in the ADC sampling clock (typically no more
than ±25ppm). If synchronization of the ADCs’ sampling clock frequency with an external reference
is desired, the External Clock input can be driven with a 10 MHz source. This is commonly available
at the back of many signal generators and is the reference to which output sine waves from the
signal generator are locked. Supplying this 10 MHz reference to the External Clock Input will
precisely lock the FSF-AD8200A ADC sampling clocks to the 10 MHz reference frequency. This
capability is useful when post-capture FFT analysis is to be performed on sine wave inputs applied to
the ADCs. If you would like to learn more about this capability, contact Fidus Systems for related
documentation or assistance with other synchronization options.
6.4
External Trigger Input
The External Trigger SSMC connector input (labeled “TR”) is terminated in a shunt 4.12kΩ resistor
and ESD protection device. The signal is DC-coupled to a buffer gate that sends its output through a
22Ω series termination directly to the FMC connector.
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