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ATLAS TDAQ 0
Version/Issue: 10/6
Contents
1INTRODUCTION.........................................................................................5
1.1GLOSSARY, ACRONYMS AND ABBREVIATIONS...................................................5
1.2REFERENCES....................................................................................................5
2BOARD DESCRIPTION................................................................................5
3CONFIGURATION.......................................................................................7
3.1JTAG CONFIGURATION.....................................................................................7
3.1.1CPLD configuration....................................................................................................7
3.1.2FPGA configuration....................................................................................................7
4POWER-ON CONFIGURATION....................................................................8
5PARALLEL CONFIGURATION....................................................................10
6LED BLOCK...............................................................................................11
7CLOCK RESSOURCES................................................................................11
8CONTROL CPLD........................................................................................12
8.1SWITCHES......................................................................................................12
9BRIDGE FPGA...........................................................................................12
9.1FPGA..............................................................................................................12
9.2SDRAM...........................................................................................................12
9.3ETHERNET......................................................................................................12
9.4SERIAL PORT..................................................................................................12
9.5CPLD INTERFACE............................................................................................13
9.6FLASH INTERFACE..........................................................................................13
9.7PROGRAMMABLE CLOCKS................................................................................13
9.8PCIE / PCI-X...................................................................................................13
10MAIN FPGA............................................................................................14
10.1SRAM BANKS................................................................................................14
10.2DRAM BANK..................................................................................................14
10.3MEZZANINE INTERFACE................................................................................14
10.3.1Interface signals....................................................................................................14
10.3.2Power supply........................................................................................................14
10.4BOARD-TO-BOARD INTERFACE......................................................................14
11REFERENCE DESIGNS............................................................................15
11.1DESIGN RULES..............................................................................................15
11.2CONFIGURATION..........................................................................................15
11.2.1CfgTest ................................................................................................................15
12APPENDIX..............................................................................................16
12.1MGT NUMBERING SCHEME............................................................................16
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