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X8OBN-F Platform with X8OBN-F Baseboard X8OBN-CPU CPU Board X8OBN-BR1 Bridge Card USER’S MANUAL Revision 1.1b The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note: For the most up-to-date version of this manual, please see our Website at www.supermicro.com. Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software and documentation, is the property of Supermicro and/or its licensors, and is supplied only under a license. Any use or reproduction of this product is not allowed, except as expressly permitted by the terms of said license. IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC. SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA. Any disputes arising between the manufacturer and the customer shall be governed by the laws of Santa Clara County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product. FCC Statement: This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the manufacturer’s instruction manual, may cause harmful interference with radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case you will be required to correct the interference at your own expense. California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”. WARNING: Handling of lead solder materials used in this product may expose you to lead, a chemical known to the State of California to cause birth defects and other reproductive harm. Manual Revision 1.1b Release Date: Oct. 24, 2012 Unless you request and receive written permission from Super Micro Computer, Inc., you may not copy any part of this document. Information in this document is subject to change without notice. Other products and companies referred to herein are trademarks or registered trademarks of their respective companies or mark holders. Copyright © 2012 by Super Micro Computer, Inc. All rights reserved. Printed in the United States of America Preface Preface This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the X8OBN-F platform, which consists of the X8OBN Baseboard, the X8OBN-CPU Board, and the X8OBN-BR1 Bridge Card. Note: CPU card and CPU board, Bridge card and Bridge board are used interchangeably in this manual. About the X8OBN-F Platform The X8OBN-F platform consists of the X8OBN Baseboard, the X8OBN-CPU CPU Board, and the X8OBN-BR1 Bridge Card. Each X8OBN-CPU Board supports up to two Intel 7500 series processors and 16 DDR3 1066MHz memory modules. The Intel 7500 series processors offer Intel QuickPath Interconnect (QPI) Technology, providing point-to-point system interface that replaces Front Side Bus technology. The X8OBN-BR Bridge card provides connections between a pair of the CPU boards installed on the X8OBN Baseboard. With support of Intel Turbo Boost Technology and up to 80 CPU cores, the X8OBN-F platform offers substantial enhancement in system performance for 4-way and 8-way servers. Please refer to our Website at http://www.supermicro.com for processor and memory support updates. This product is intended to be installed and serviced by professional technicians. Manual Organization Chapter 1 provides quick installation instructions. Chapter 2 describes the features, specifications and performance of the X8OBN-F baseboard, and provides detailed information on the 7500 chipset. Chapter 3 provides hardware installation instructions. Read this chapter when installing the processor, memory modules and other hardware components into the system. If you encounter any problems, see Chapter 4, which describes troubleshooting procedures for video, memory and system setup stored in CMOS. Chapter 5 includes an introduction to BIOS and provides detailed information on running the CMOS Setup Utility. Appendix A provides BIOS Error Beep Codes. Appendix B lists software installation instructions. iii X8OBN-F Platform User’s Manual Conventions Used in this Manual Pay special attention to the following symbols for proper baseboard installation and to prevent damage to the system or injury to yourself: Danger/Caution: Instructions to be strictly followed to prevent catastrophic system failure or to avoid bodily injury, Warning: Important information given to ensure proper system installation or to prevent damage to the components, Note: Additional information given to differentiate between various models or to provide information for correct system setup. iv Preface Contacting Supermicro Headquarters Address: Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: [email protected] (General Information) [email protected] (Technical Support) Web Site: www.supermicro.com Europe Address: Super Micro Computer B.V. Het Sterrenbeeld 28, 5215 ML 's-Hertogenbosch, The Netherlands Tel: +31 (0) 73-6400390 Fax: +31 (0) 73-6416525 Email: [email protected] (General Information) [email protected] (Technical Support) [email protected] (Customer Support) Asia-Pacific Address: Super Micro Computer, Inc. 4F, No. 232-1, Liancheng Rd New Taipei City 235 Taiwan Tel: +886-(2) 8226-3990 Fax: +886-(2) 8226-3991 Web Site: www.supermicro.com.tw Technical Support: Email: [email protected] Tel: +886-(2)-8226-3990 v X8OBN-F Platform User’s Manual Table of Contents Preface Chapter 1 Quick Installation Guide 1-1 Preparation for Proper System Installation...................................................... 1-1 Removing the Bridge Module from the Chassis.............................................. 1-1 Removing the CPU Module from the Chassis................................................. 1-1 Attaching the Bridge Card to the Bridge Card Plate............................................ Attaching the CPU Board to the CPU Board Plate.............................................. Installing the I/O Shield on the Rear Side of the Chassis.................................... 1-2 Installing the CPU on the CPU Board............................................................. 1-2 1-3 Installing the Memory Module on the CPU Board........................................... 1-2 1-4 Installing the CPU Heatsink on the CPU Board.............................................. 1-3 1-5 Attaching the Air Shroud on the CPU Module................................................. 1-3 1-6 Installing the Baseboard into the Chassis....................................................... 1-4 1-7 Installing the CPU Module on the Baseboard................................................. 1-5 1-8 Installing the Bridge Board between the CPU Boards.................................... 1-6 1-9 Installing Internal Peripherals........................................................................... 1-7 1-10 Installing External Peripherals......................................................................... 1-8 Chapter 2 Overview 2-1 Overview.......................................................................................................... 2-1 2-2 Chipset Overview........................................................................................... 2-13 2-3 Special Features............................................................................................ 2-14 2-4 PC Health Monitoring..................................................................................... 2-14 2-5 ACPI Features................................................................................................ 2-15 2-6 Power Supply................................................................................................. 2-15 2-7 Super I/O........................................................................................................ 2-16 2-8 Overview of the Nuvoton WPCM450R Controller ........................................ 2-16 Chapter 3 Installation 3-1 Standardized Warning Statements.................................................................. 3-1 Battery Handling............................................................................................... 3-1 Product Disposal.............................................................................................. 3-3 3-2 Static-Sensitive Devices................................................................................... 3-4 Precautions...................................................................................................... 3-4 Unpacking........................................................................................................ 3-4 3-3 Populating the CPU Board............................................................................... 3-5 Installing a CPU on the CPU Board................................................................ 3-5 Installing the CPU Heatsink on the CPU Board.............................................. 3-6 Installing Memory Modules on the CPU Board............................................... 3-7 vi Table of Contents Removing Memory Modules............................................................................ 3-7 3-4 Installing the Baseboard into the Chassis....................................................... 3-8 Tools Needed................................................................................................... 3-8 3-5 Installing the Populated CPU Board on the Baseboard.................................. 3-9 3-6 Installing the Bridge Card between the CPU Boards.................................... 3-10 3-7 Memory Support for the X8OBN-F Platform...................................................3-11 3-8 Control Panel Connectors/I/O Ports.............................................................. 3-13 Back Panel Connectors/I/O Ports.................................................................. 3-13 Back Panel I/O Port Locations and Definitions ............................................ 3-13 ATX PS/2 Keyboard and PS/2 Mouse Ports............................................. 3-14 Universal Serial Bus (USB)....................................................................... 3-15 Serial Ports................................................................................................ 3-16 Video Connection...................................................................................... 3-16 Ethernet Ports........................................................................................... 3-17 Unit Identifier Switch................................................................................. 3-18 Front Control Panel........................................................................................ 3-19 Front Control Panel Pin Definitions............................................................... 3-20 NMI Button................................................................................................ 3-20 Power LED ............................................................................................... 3-20 HDD LED................................................................................................... 3-21 NIC1/NIC2 LED Indicators........................................................................ 3-21 Overheat (OH)/Fan Fail/PWR Fail/UID LED............................................. 3-22 Power Fail LED......................................................................................... 3-22 Reset Button ............................................................................................ 3-23 Power Button ............................................................................................ 3-23 3-9 Connecting Cables......................................................................................... 3-24 Power Connectors .................................................................................... 3-24 DOM Power Connector............................................................................. 3-24 Fan Headers.............................................................................................. 3-25 Chassis Intrusion ...................................................................................... 3-25 Internal Buzzer.......................................................................................... 3-26 Power LED/Speaker.................................................................................. 3-26 TPM Header/Port 80................................................................................. 3-27 Overheat LED/Fan Fail............................................................................. 3-27 T-SGPIO 1/2 Headers............................................................................... 3-28 3-10 Jumper Settings............................................................................................. 3-29 Explanation of Jumpers................................................................................. 3-29 GLAN Enable/Disable............................................................................... 3-29 CMOS Clear.............................................................................................. 3-30 vii X8OBN-F Platform User’s Manual Watch Dog Enable/Disable....................................................................... 3-30 VGA Enable............................................................................................... 3-31 TPM Support Enable................................................................................. 3-31 BMC Enable ............................................................................................. 3-32 ME Recovery ............................................................................................ 3-32 Manufacturer Mode Select........................................................................ 3-33 JUID_OW1 (UID_Overwriting).................................................................. 3-33 BMC Reset ............................................................................................... 3-34 3-11 Onboard LED Indicators................................................................................ 3-35 GLAN LEDs............................................................................................... 3-35 IPMI Dedicated LAN LEDs........................................................................ 3-35 Rear UID LED .......................................................................................... 3-36 BMC Heartbeat LED................................................................................. 3-36 3-12 Serial ATA Connections.................................................................................. 3-37 Serial ATA Ports........................................................................................ 3-37 Chapter 4 Troubleshooting 4-1 Troubleshooting Procedures............................................................................ 4-1 4-2 Technical Support Procedures......................................................................... 4-4 4-3 Frequently Asked Questions............................................................................ 4-5 4-4 Returning Merchandise for Service................................................................. 4-6 Chapter 5 BIOS 5-1 Introduction....................................................................................................... 5-1 5-2 Main Setup....................................................................................................... 5-2 5-3 Advanced Setup Configuration........................................................................ 5-4 5-4 Chipset........................................................................................................... 5-19 5-5 Server Management....................................................................................... 5-27 5-6 iSCSI.............................................................................................................. 5-29 5-7 Boot Configuration......................................................................................... 5-29 5-8 Security.......................................................................................................... 5-31 5-9 Save & Exit.................................................................................................... 5-32 Appendix A BIOS Error Beep Codes A-1 BIOS Error Beep Codes..................................................................................A-1 Appendix B Software Installation Instructions B-1 Installing Software Programs...........................................................................B-1 B-2 Configuring SuperDoctor III.............................................................................B-2 viii Chapter 1: Quick Installation Guide Chapter 1 Quick Installation Guide If you purchase a bare bone system from Supermicro, the X8OBN-F Baseboard, the X8OBN-CPU CPU Module, which includes the CPU board and its accessory, and the X8OBN-BR1 Bridge Module, which includes a bridge board and its accessory, are enclosed in the chassis. To prepare your system for proper installation, follow the instructions below. 1-1 Preparation for Proper System Installation Removing the Bridge Module from the Chassis 1. Loosen the screws on the Bridge board bracket. 2. Using even pressure pull the Bridge module out of the CPU module. Removing the CPU Module from the Chassis 1. Locate the red latches on the handles of the CPU module 2. Press both red latches outwards (towards the ends of the chassis) to release the CPU module handle from its locking position. 3. Hold both handles of the CPU board upwards to gently pull the CPU board out from the chassis. A Press the red latches outwards to unlock the CPU Board B Pull the handles upwards to remove the CPU Board from the chassis. Note 1. All graphics and images are for illustration only. They may be different from what you have in your system. Note 2. CPU card and CPU board, Bridge card and Bridge board are used interchangeably in this manual. 1-1 X8OBN-F Platform User's Manual 1-2 Installing the CPU on the CPU Board 2 A B 1 A. Press the socket clip down to unlock it. Gently lift the socket clip to open the load plate. CPU Key B. Align the CPU key with the socket key. D C CPU Pin 1 C. Align CPU Pin 1 against Socket Pin 1. Once they are aligned, lower the CPU down to the socket. D. Once the CPU is fully seated on the socket, press the socket clip down to lock it. To avoid damaging the CPU, do not rub the CPU pins against the socket. 1-3 Installing the Memory Module on the CPU Board A B C A. Align the key on the DIMM module against the key of the DIMM socket. B. Insert the DIMM module straight down to the DIMM socket by pressing both ends of the DIMM module at the same time. 1-2 C. Press the notches on the ends of the DIMM module inwards to lock it. Chapter 1: Quick Installation Guide 1-4 Installing the CPU Heatsink on the CPU Board A B A. If needed, apply the proper amount of thermal grease (with thickness of up to 0.13 mm) to the heatsink. B. Place the heatsink on top of the CPU so that the two mounting holes on the heatsink are aligned with those on the retention mechanism. Note: The proper amount of thermal grease has been applied to our heatsinks. If you use a heatsink purchased from SMC, skip this step. C. Insert two push-pins on the sides of the heatsink through the mounting holes on the motherboard, and turn the push-pins clockwise to lock them. 1-5 Attaching the Air Shroud on the CPU Module Populated CPU Board (w/Air Shroud) Populated CPU Board (w/Air Shroud) (Side View) 1-3 Populated CPU Board (w/Air Shroud) (Side View) Attach the air shroud on the CPU module before you install the CPU module on the X8OBN baseboard, making sure that all four hooks of the air shroud are fully engaged. X8OBN-F Platform User's Manual 1-6 Installing the Baseboard into the Chassis Follow the steps below to install the baseboard into the chassis. Be sure to install the IO shield on the rear side of the chassis before you install the baseboard. A. Locate the release latch on the handle of the power distributor. Press the release latch to release Image will be placed when available B the power distributor from locking position. C LS LS JWD1 JOH1 X8OBN-F Baseboard KB/Mouse B. Push the handle of the power distributor forwards to make room for the main board to be installed. USB 0/1 JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 Fan 10 Fan 9 LAN CTRL LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 UID JPL1 D. Install standoffs in the chassis as needed and secure the baseboard to the standoffs with screws. CPU Board Slot 2 J32 J25 LED6 LAN2 LAN1 C. Locate the mounting holes (23) on the baseboard. Fan4 JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 PLX PCI Bridge Battery JPWR2 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME1 ICH10R Slot1 PCI-E 2.0 x8 in x16 USB4/5 USB2/3 Slot2 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 PWR 2 BT1 JPME2 JPB1 JPRST1 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 E. Place the baseboard in the chassis making sure that the mounting holes on the baseboard match the corresponding standoffs on the chassis. Please note that there are three locating standoffs in the chassis as shown in the drawing. Be sure that the main board is fully seated on these locating standoffs. J26 Slot6 PCI-E 2.0 x16 T-SGPIO2 BMC CTRL PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 LED4 JL1 JP21 T-SGPIO1 LS Locating Standoff D Image will be placed when available E Note: Mounting Holes marked with LS are for locating standoffs. F. Pull the handle of the power distributor backward to connect it to the base board. G. Connect the HDD Power Connector cables to the power supply through an opening on the middle fan plate. G Image will be placed when available H Image will be placed when available H. Connect the intrusion cable and the Front Panel Control cable. X8OBN BaseBoard in the Chassis 1-4 Chapter 1: Quick Installation Guide 1-7 Installing the CPU Module on the Baseboard After populating the CPU board with needed components, and installing the baseboard in the chassis, you can install the CPU module on the baseboard. A. Using two hands, hold both handles of the CPU module. B. Locate the CPU board slots on the X8OBN baseboard. Insert a CPU module into a CPU board slot by following the steps below, starting from Slot1. 1. Align the guiding edges of the CPU bracket against the guiding rails on the middle fan bracket and on the rear window of the chassis. 2. Insert the CPU module into the baseboard until the bottom of the CPU board contacts the top of the CPU slot. 3. Press both handles of the CPU board inwardly to close them. Then, gently push the CPU board into the CPU board slot until the CPU board is fully seated in the CPU slot. 4. Press the red latches on the handles of the CPU bracket to lock the CPU module onto the baseboard. A X8OBN-F Baseboard Rev. 1.01 CPU Board Slot4 CPU Board Slot3 CPU Board Slot2 CPU Board Slot1 B X8OBN Baseboard Populated CPU Board (w/Air Shroud) D CPU Board CP Ba se Bo ar UB oa rd Slo t d 1-5 X8OBN-F Platform User's Manual 1-8 Installing the Bridge Board between the CPU Boards Once you've installed the CPU modules on the baseboard, you can install the X8OBN-BRI Bridge board on the CPU boards. Note: A Bridge board is needed to connect the pair(s) of the CPU boards installed on Slot1 & Slot2, and/or Slot3 & Slot4. There is no Bridge board needed between Slot2 and Slot3. Refer to the table below for details. CPU Board on Slot1 CPU Board on Slot2 CPU Board on Slot3 CPU Board on Slot4 X8OBN-BRI Bridge Board to be Installed Memory Support Yes Yes No No One card needed between Slot1 & Slot2 16/32 DIMMs Yes Yes Yes Yes One card needed between Slot1 & Slot2; Another card needed between Slot3 & Slot4 32/64 DIMMs To install the Bridge board between the CPU boards, follow the steps below: A. Place the Bridge module on top of the CPU boards, making sure that the slot on the Bridge board matches the golden finger of the CPU boards. B. Press the module evenly to ensure that the gold fingers of the CPU boards are fully seated on the Bridge board slots. Double check to make sure that all Bridge modules are aligned horizontally after installation. Brid X8OBN-BR1 Bridge Card ard ge C To Connect to the CPU Board Popu lated Boar CPU h d wit hro Air S ud Two Bridge Cards Four CPU Boards 1-6 Chapter 1: Quick Installation Guide 1-9 Installing Internal Peripherals A B SATA Drives Add-on Cards 1. Remove screws from the assembly. 2. Pull the AC plug cage out of the chassis. 3. Remove the L bracket. 4. Install add-on cards. 5. Install screws and lock add-on cards. 6. Insert the add-on card assembly properly into the chassis. 7. Secure it to the chassis with screws. 1-7 X8OBN-F Platform User's Manual 1-10 Installing External Peripherals Mouse IPMI LAN Keyboard USB 0/1 COM1 VGA LAN1 LAN 2 UID Switch Notes: 1. All graphics and images are for illustration only. They may be different from what you have in your system. 2. For more details on power cable connection, please refer to Section 3-8 in Chapter. Also refer to Chapter 3 for more information on system installation. 1-8 Chapter 2: Overview Chapter 2 Overview 2-1 Overview Checklist Congratulations on purchasing your computer system from an acknowledged leader in the industry. Supermicro systems are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. For more information regarding this product, please visit our website at www. supermicro.com. 2-1 X8OBN-F Platform User’s Manual X8OBN-F Baseboard Image Note: All graphics shown in this manual were based upon the latest PCB Revision available at the time of publishing of the manual. The board you've received may or may not look exactly the same as the graphics shown in this manual. 2-2 Chapter 2: Overview X8OBN-F Baseboard Layout JWD1 JOH1 KB/Mouse X8OBN-F Baseboard JF1 Fan6 IPMI LAN USB 0/1 COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 CPU Board Slot 2 Fan 10 Fan 9 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 UID JPL1 LED6 LAN2 LAN1 Fan4 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 JD1 Slot3 PCI-E 2.0 x8 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 BT1 JBT1 JPME2 JPB1 JPRST1 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 I-SATA2 I-SATA0 T-SGPIO2 BMC CTRL JPG1 LED4 PWR 1 I/O Hub 2 JL1 JP21 T-SGPIO1 Notes: •See Chapter 3 for detailed information on jumpers, I/O ports and JF1 front panel connections. •" " indicates the location of "Pin 1". •Jumpers not indicated are for testing only. •LED Indicators that are not documented are for testing only. •Please refer to the quick installation guide in Chapter 1 and installation instructions listed in Chapter 3 for installation instructions. 2-3 X8OBN-F Platform User’s Manual X8OBN-CPU Board Image X8OBN-CPU Board Layout X8OBN-CPU Rev.1.01 J47 J48 P2-DIMM6A P1-DIMM4A P2-DIMM5A P1-DIMM3A MB3 (for CPU2) MB4 (for CPU2) MB2 (for CPU1) CPU2 MB1 (for CPU1) P1-DIMM1A P2-DIMM7A P1-DIMM2A P2-DIMM8A P2-DIMM2A P1-DIMM8A P2-DIMM1A P1-DIMM7A MB1 (for CPU2) MB2 (for CPU2) CPU1 MB4 (for CPU1) P2-DIMM3A MB3 (for CPU1) P1-DIMM5A P1-DIMM6A P2-DIMM4A J35 J43 J44 J46 2-4 J45 J36 Chapter 2: Overview X8OBN-BR1 Bridge Card Image 2-5 X8OBN-F Platform User’s Manual X8OBN-F Baseboard Layout KB/Mouse FP CRTL JF1 Fan6 Rev. 1.01 IPMI LAN USB 0/1 COM1 JWD1 JOH1 X8OBN-F Baseboard CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 Fan 10 Fan 9 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 UID J32 J25 CPU Board Slot 2 JPL1 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 JPB1 LED6 LAN2 LAN1 Fan4 JL1 JP21 T-SGPIO1 Note: Due to PCI-E auto-switching, please follow the instructions below. •For PCI-E 2.0 Slot 10 and Slot 9: Install Slot 10 first. However, Slot 10 will be down-graded to support a PCI-E 2.0 x8 device when Slot 9 is populated with a PCI-E 2.0x8 device. •For PCI-E 2.0 Slot 8 and Slot 7: Install Slot 8 first. However, Slot 8 will be down-graded to support a PCI-E 2.0 x8 device when Slot 7 is populated with a PCI-E 2.0x8 device. •For PCI-E 2.0 Slot 6 and Slot 5: Install Slot 6 first. However, Slot 6 will be down-graded to support a PCI-E 2.0 x8 device when Slot 5 is populated with a PCI-E 2.0x8 device. •For PCI-E 2.0 Slot 4 and Slot 3: Install Slot 4 first. However, Slot 4 will be down-graded to support a PCI-E 2.0 x8 device when Slot 3 is populated with a PCI-E 2.0x8 device. 2-6 Chapter 2: Overview X8OBN-F Baseboard Quick Reference X8OBN-F Jumpers Jumper Description Default Setting JBT1 Clear CMOS See Chapter 3 JPB1 BMC Enabled Pins 1-2 (Enabled) JPG1 VGA Enabled Pins 1-2 (Enabled) JPME1 ME Mode Recovery Off (Normal) JPME2 ME Mode Select Off (Normal) JPL1 GLAN1/GLAN2 Enable Pins 1-2 (Enabled) JPRST1 BMC Reset Off (Normal) JPT1 TPM Enabled Pins 1-2 (Enabled) JUID_OW1 UID Overwrite Off (Normal) JWD1 Watch Dog Pins 1-2 (Reset) X8OBN-F Baseboard Connectors Connectors Description 3-pin Fans (Two) 3-pin Fan Headers for IOH1 (Fan7) & IOH2 (Fan8) 4-pin Fans (Six) 4-pin System/Cooling Fan Headers (Fan1/Fan2, Fan9~Fan 12) (Four) 4-pin CPU_Board Fan Headers (Fan3~Fan6) BT1 Onboard Battery (See Chpt. 4 for Used Battery Disposal) Buzzer Internal Buzzer CPU Board Slots 1~4 CPU Board Slots 1~4 (for CPU boards) COM1/COM2 COM/Serial Connections I-SATA 0~5 Intel SB SATA Connectors 0~5 JD1 Speaker/Power LED Indicator JF1 Front Panel Control Header JIPMB1 4-pin External BMC I2C Header (for an IPMI Card) JL1 Chassis Intrusion JOH1 Overheat/Fan Fail LED JP16~JP19 HDD Power Connectors (See Warning on Pg. 2-8) JP21/JP22 Main Power supply Connectors (JP22: PWR1/JP21: PWR2) (See Warning on Pg. 2-8) JPWR1~JPWR4 8-Pin GPU Power Connectors (Warning on Pg. 2-8.) JTPM1 TPM (Trusted Platform Module)/Port 80 Header JWF1 SATA DOM (Device_On-Module) Power Connector (See Warning on Pg. 2-8) KB/MOUSE Keyboard/Mouse Connections 2-7 X8OBN-F Platform User’s Manual LAN1/LAN2 G-bit Ethernet Ports 1/2 (IPMI) LAN IPMI_Dedicated LAN PCI-E 2.0 x8 PCI-Express 2.0 x8 Slots (Slot3/Slot5/Slot7/Slot9)(See Note on P. 2-6) PCI-E 2.0 x8 in x16 PCI-Express 2.0 x8 in x16 Slots (Slot1/Slot2) (See Note on P. 2-6) PCI-E 2.0 x16 PCI-Express 2.0 x16 Slots (Slot4/Slot6/Slot8/Slot10) (See Note on P. 2-6) T-SGPIO 1/2 Serial_Link General Purpose I/O Headers USB 0/1 Back Panel USB 0/1 USB 2/3, USB 4/5, USB 8, USB 10 Front Panel Accessible USB Connections UID Switch UID (Unit Identifier) Switch VGA Backpanel VGA Port X8OBN-F LED Indicators LED Description State Status LED4 BMC Heartbeat LED Green: Blinking Normal LED 6 UID LED Blue: On (Windows OS), UID LED Blinking (Linux) LED12~LED19 Port 80 LEDs 8-bit binary POST Code (for future LEDs debug) Note: For PCI-E slots to work properly, follow the instructions listed on Page 2-6. Warning! To avoid damaging the power supply or the system, and to provide adequate power to the components, be sure to connect the main power connectors (JP22, JP21) and the following power connectors to the power supply. Failure to do so will void the manufacturer warranty. •Main Power Connectors (JP22, JP21). •HDD Power Connectors (reserved for HDD used only) (JP16~JP19) •GPU 8-pin Power Connectors (reserved for graphics card use only) (JPWR1/ JPWR2/JPWR3/JPWR4) •SATA DOM Power Connector used for SATA devices (JWF1) 2-8 Chapter 2: Overview Baseboard Features Baseboard Modular design with a baseboard with four CPU_board slots that support up to four CPU boards; 1. The baseboard includes two 7500 IO hubs, one PLX PEX8648 PCI-E software controller and ten PCI-E slots; 2. Each CPU board includes the following: CPU (per CPU Board) Memory (per CPU Board) • Two Intel® 7500 Series (Socket LS-LGA 1567) processors; each processor supports four full-width Intel QuickPath Interconnect (QPI) links (with support of up to 25.6 GT/s per QPI link and with Data Transfer Rate of up to 6.4 GT/s per direction) •16 DDR3R RDIMMs running at speeds of 1066/978/800 MHz (via an onboard buffer) •Support for up to 256 GB of Registered ECC DDR3 memory per CPU board • RDIMM Chipset Expansion Slots (See Page 2-6) Graphics Network 1GB, 2GB, 4GB, 8GB, 16GB and 32 Gb • Two Intel® 7500 IO Hubs • One ICH10R • Four (4) PCI E 2.0 x8 (Slot3/Slot5/Slot7/Slot9) • Two (2) PCI E 2.0 x8 in x16 (Slot1/Slot2) • Four (4) PCI E 2.0 x16 (Slot4/Slot6/Slot8/Slot10) • Winbond BMC Video Controller (Matrox G200eW) • One Intel 82576 Gigabit (10/100/1000 Mb/s) Ethernet Dual-Channel Controller for LAN 1/LAN 2 ports. •One IPMI LAN 2.0 port supported by the BMC I/O Devices SATA Connections • SATA Ports • R A I D ( W i n - Six (6) RAID 0, 1, 5, 10 dows) Integrated IPMI 2.0 • IPMI 2.0 supported by the WPCM450R BMC Serial (COM) Port • Two (2) Fast UART 16550 Connections: a Backplane Serial Port and a Front Accessible Serial Header 2-9 X8OBN-F Platform User’s Manual Super I/O • Winbond Super I/O 83527 Peripheral Devices USB Devices • Two (2) USB ports on the rear I/O panel (USB 0/1) • Two (2) USB connectors (4 ports) for front access (USB 2/3, USB 4/5) BIOS • Two (2) Type A internal connector (USB 8/10) • 64 Mb SPI AMI BIOS® SM Flash BIOS • APM 1.2, PCI 2.3, ACPI 1.0/2.0/3.0, USB Keyboard, Power • Two Plug & Play (PnP) and SMBIOS 2.5 (2) Main Power Supply Connectors (PWR1/ PWR2) • F o u r (4) 8-pin GPU Power Connectors (JPWR1~JPWR4), 3. Four (4) HDD Power Connectors (JP16/JP17/JP18/ JP19) • One (1) SATA DOM Power Connection (JWF1) Note: All these power connections are required for adequate power supply to the components and the system. Config. PC Health Monitoring • ACPI/ACPM Power Management • Main switch override mechanism • Power-on mode for AC power recovery CPU Monitoring Onboard voltage monitors for CPU Vcore (up to 8 CPUs), IOH1 Vcore, IOH2 Vcore, 3.3VDD, 3.3VSB, P3V3, P3V3_AUX, 12V, 5V, Memory Voltage, and Battery Voltage. • CPU 7-Phase switching voltage regulator • CPU/System overheat LED and control • CPU Thermal Trip support • Thermal Monitor 2 (TM2) support 2-10 Chapter 2: Overview Fan Control • Twelve (12) 4-pin system cooling fans with Fan status monitoring with firmware (Pulse Width Modulation) fan speed control and Low noise fan speed control • Two (2) 3-pin IOH fans (JP3: IOH1 Fan/JP2: IOH2 Fan) System Management Dimensions • PECI (Platform Environment Configuration Interface) 2.0 support • System resource alert via SuperDoctor III • SuperDoctor III, Watch Dog, NMI • Chassis Intrusion Header and Detection • 16.8" (L) x 16.4" (W) (426.72mm x 416.56 mm) (X8OBN-F Baseboard) Notes: 1. For IPMI Configuration Instructions, please refer to the Embedded IPMI Configuration User's Guide available @ http://www.supermicro.com/support/ manuals/. 2. For PCI-E expansion slots to work properly, please refer to the instructions listed on Page 2-6. 2-11 QPI 6.4GT/s 2-12 GLAN RJ45 CONN GLAN RJ45 CONN KAWELA Slot7 PCI-e x8 (X8) Slot8 PCI-e x16 (X16) Slot9 PCI-e x8 (X8) Slot0 PCI-e x16 (X16) x4 MUX x8 x8 MUX x8 x8 IOH2 BOXBORO QPI 6.4GT/s QPI 6.4GT/s 10/100 RJ45 x8 KB/MS Connector COM2 Header COM1 Connector VGA Connector 10/100 PHY Slot1 PCI-e x16 (x8) x8 x8 MUX TPM Internal Hheader TPM SLB9635 SIO W83527HG BMC WPCM450 PEX8648 PCI-E BRIDGE LPC PCI 32/33 CPU3 USB 2.0 x4 USB 2.0 x2 CPU1 HWM W83795ADG SM BUS SPI SATA ICH10R USB 2.0 x2 ESI (x4) ESI (x4) IOH1 BOXBORO USB 2.0 X2 x16 x8 x8 x8 MUX Slot6 PCI-e x16 (x16) Slot5 PCI-e x8 (x8) Slot2 PCI-e x16 (x8) Slot3 PCI-e x8 (x8) Slot4 PCI-e x16 (x16) QPI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.E MB2 SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.F DDR3 800/1066 * 1 DDR3 Ch.G MB3 SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.H QPI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.A MB0 SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.B DDR3 800/1066 * 1 DDR3 Ch.C MB1 SMI 6.4GT/s CPU0 QPI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.D QPI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.G MB3 SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.H DDR3 800/1066 * 1 DDR3 Ch.A MB0 SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.B DDR3 800/1066 * 1 DDR3 Ch.C MB1 SMI 6.4GT/s CPU2 DDR3 800/1066 * 1 DDR3 Ch.D DDR3 800/1066 * 1 DDR3 Ch.E MB2 SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.F QPI 6.4GT/s QPI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.A MB0 SMI 6.4GT/s SMI 6.4GT/s MB0 DDR3 Ch.A DDR3 800/1066 * 1 DDR3 Ch.B DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.B DDR3 Ch.C SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.C MB1 SMI 6.4GT/s MB1 DDR3 Ch.D DDR3 800/1066 * 1 CPU4 QPI 6.4GT/s CPU5 DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.D DDR3 800/1066 * 1 DDR3 Ch.E MB2 SMI 6.4GT/s SMI 6.4GT/s MB2 DDR3 Ch.E DDR3 800/1066 * 1 DDR3 Ch.F DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.F DDR3 800/1066 * 1 DDR3 Ch.G MB3 SMI 6.4GT/s SMI 6.4GT/s MB3 DDR3 Ch.G DDR3 800/1066 * 1 DDR3 Ch.H DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.H QPI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.G MB3 SMI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.H QPI 6.4GT/s DDR3 Ch.A DDR3 800/1066 * 1 DDR3 Ch.B DDR3 800/1066 * 1 DDR3 Ch.C DDR3 800/1066 * 1 DDR3 Ch.D DDR3 800/1066 * 1 DDR3 Ch.E DDR3 800/1066 * 1 DDR3 Ch.F DDR3 800/1066 * 1 SMI 6.4GT/s MB3 DDR3 Ch.G DDR3 800/1066 * 1 DDR3 Ch.H DDR3 800/1066 * 1 QPI 6.4GT/s DDR3 800/1066 * 1 DDR3 Ch.A MB0 SMI 6.4GT/s SMI 6.4GT/s MB0 DDR3 800/1066 * 1 DDR3 Ch.B DDR3 800/1066 * 1 DDR3 Ch.C MB1 SMI 6.4GT/s SMI 6.4GT/s MB1 DDR3 Ch.D CPU6 QPI 6.4GT/s CPU7 DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.E MB2 SMI 6.4GT/s SMI 6.4GT/s MB2 DDR3 800/1066 * 1 DDR3 Ch.F DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 800/1066 * 1 12 * FAN SPI BIOS 6 * SATA Connectors Stack 2 Ports USB Connector 2 * USB 2 Ports Internal Headers 2 * USB Type A Internal Connectors DDR3 800/1066 * 1 DDR3 800/1066 * 1 SMI 6.4GT/s MB3 DDR3 Ch.G DDR3 800/1066 * 1 DDR3 Ch.H DDR3 800/1066 * 1 SMI 6.4GT/s MB2 DDR3 Ch.E DDR3 Ch.F SMI 6.4GT/s MB0 DDR3 Ch.A DDR3 Ch.B SMI 6.4GT/s MB1 DDR3 Ch.C DDR3 Ch.D DDR3 Ch.A SMI 6.4GT/s MB0 DDR3 Ch.B DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.C SMI 6.4GT/s MB1 DDR3 Ch.D DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.E SMI 6.4GT/s MB2 DDR3 Ch.F DDR3 800/1066 * 1 DDR3 800/1066 * 1 DDR3 Ch.G SMI 6.4GT/s MB3 DDR3 Ch.H DDR3 800/1066 * 1 DDR3 800/1066 * 1 X8OBN-F Platform User’s Manual System Block Diagram Note: This is a general block diagram and may not exactly represent the features on your baseboard. See the Baseboard Features pages for the actual specifications of each baseboard. Chapter 2: Overview 2-2 Chipset Overview Built upon the functionality and the capability of the Intel 7500 platform, the X8OBN-F baseboard provides the performance and support for eight-processorbased HPC/Cluster/Database servers. The 7500 platform consists of the 7500 Series Socket-LS (LGA 1567) processor, the 7500 (IOH), and the ICH10R (South Bridge). With the Intel QuickPath interconnect (QPI) controller built in, the 7500 Series processor offers point-to-point system interconnect interface, greatly enhancing system performance by utilizing serial link interconnections, allowing for increased bandwidth and scalability. The IOH provides the interface between QPI-based processor and PCI-Express components. Each processor supports four full-width, bidirectional interconnects at the speed of 4.8 GT/s, 5.86 GT/s or 6.4 GT/s. Each QPI link consists of 20 pairs of unidirectional differential lanes for data transmission in addition to a differential forwarding clock. The x16 PCI Express Gen 2 connections can also be configured as x8, x4, x2, x1 links to comply with the PCI-E Base Specification, Rev. 2.0. These PCI-E Gen 2 lanes support peer-to-peer read and write transactions. In addition, the legacy IOH provides a x4 ESI (Enterprise South Bridge Interface) link support for the legacy bridge. The 7500 chipset also offers a wide range of ESI, Intel® I/OAT Gen 3, Intel VT-d and RAS (Reliability, Availability and Serviceability) support. The features supported include memory interface ECC, x4/x8 Single Device Data Correction (SDDC), Flow-through CRC (Cyclic Redundancy Check), parity protection, out-ofband register access via SMBus, and memory mirroring for data integrity. Main Features of the 7500 Platform •Fully-connectivity (with four Intel® QuickPath Interconnects and up to ten cores in each socket with 24MB of shared last level (L3) cache supported) •CPU-Integrated memory controller with support of DDR-3 1066 MHz RDIMMS running at 800/978/1066 MHz via a memory buffer •Virtualization Technology •44 bits physical address and 48 bits virtual address supported 2-13 X8OBN-F Platform User’s Manual 2-3 Special Features Recovery from AC Power Loss Basic I/O System (BIOS) provides a setting for you to determine how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must press the power switch to turn it back on), or for it to automatically return to a power-on state. See the Advanced BIOS Setup section to change this setting. The default setting is Last State. 2-4 PC Health Monitoring This section describes the PC health monitoring features of the board. This platform has five onboard System Hardware Monitor chips that provide PC health monitoring. An onboard voltage monitor will scan these onboard voltages continuously: CPU Vcore (up to 8 CPUs), IOH1 Vcore, IOH2 Vcore, 3.3VDD, 3.3VSB, P3V3, P3V3_ AUX, 12V, 5V, Memory Voltage, and Battery Voltage. Once a voltage becomes unstable, a warning is given or an error message is sent to the screen. The user can adjust the voltage thresholds to define the sensitivity of the voltage monitor. Fan Status Monitor with Firmware Control PC health monitoring in the BIOS can check the RPM status of the cooling fans. The onboard CPU and chassis fans are controlled by Thermal Management via BIOS (under the Hardware Monitoring section in the Advanced Setting). Environmental Temperature Control The thermal control sensor monitors the CPU temperature in real time and will turn on the thermal control fan whenever the CPU temperature exceeds a user-defined threshold. The overheat circuitry runs independently from the CPU. Once the thermal sensor detects that the CPU temperature is too high, it will automatically turn on the thermal fans to prevent the CPU from overheating. The onboard chassis thermal circuitry can monitor the overall system temperature and alert the user when the chassis temperature is too high. Note: To avoid possible system overheating, please be sure to provide adequate airflow to your system. System Resource Alert This feature is available when the system is used with SuperDoctor III in the 2-14 Chapter 2: Overview Windows OS environment or used with SuperDoctor II in Linux. SuperDoctor is used to notify the user of certain system events. For example, you can also configure SuperDoctor to provide you with warnings when the system temperature, CPU temperatures, voltages and fan speeds go beyond predefined thresholds. 2-5 ACPI Features ACPI stands for Advanced Configuration and Power Interface. The ACPI specification defines a flexible and abstract hardware interface that provides a standard way to integrate power management features throughout a PC system, including its hardware, operating system and application software. This enables the system to automatically turn on and off peripherals such as CD-ROMs, network cards, hard disk drives and printers. In addition to enabling operating system-directed power management, ACPI also provides a generic system event mechanism for Plug and Play, and an operating system-independent interface for configuration control. ACPI leverages the Plug and Play BIOS data structures, while providing a processor architecture-independent implementation that is compatible with Windows XP, Windows Vista and Windows 2008 Operating Systems. Slow Blinking LED for Suspend-State Indicator When the CPU goes into a suspend state, the chassis power LED will start blinking to indicate that the CPU is in suspend mode. When the user presses any key, the CPU will "wake up" and the LED will automatically stop blinking and remain on. 2-6 Power Supply As with all computer products, a stable power source is necessary for proper and reliable operation. It is even more important for processors that have high CPU clock rates. The X8OBN-F baseboard includes two main system power connectors (JP21/22), four HDD power connectors (JP16~JP19), four GPU Power connectors (JPWR1~4), and a SATA DOM power connector (JWF1). Please connect these power connectors to the power supply to provide adequate power to the components and the system. Also your power supply must supply 1.5A for the Ethernet ports. Warning! To avoid damaging the power supply or the system, be sure to connect the Main Power connectors and other power connectors as required to the power supply. Failure to do so will void the manufacturer warranty on your power supply and the board. 2-15 X8OBN-F Platform User’s Manual It is strongly recommended that you use a high quality power supply that meets the ATX power supply Specification 2.02 or above. It must also be SSI compliant. (For more information, please refer to the website at http://www.ssiforum.org/). Additionally, in areas where noisy power transmission is present, you may choose to install a line filter to shield the computer from noise. It is recommended that you also install a power surge protector to help avoid problems caused by power surges. 2-7 Super I/O The Super I/O provides functions that comply with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through an SMI or SCI function pin. It also features auto power management to reduce power consumption. 2-8 Overview of the Nuvoton WPCM450R Controller The Nuvoton WPCM450R Controller is a Baseboard Management Controller (BMC) that supports 2D/VGA-compatible Graphics cores, Virtual Media, and Keyboard/ Video/Mouse Redirection (KVMR) modules. With blade-oriented Super I/O capability built-in, the WPCM450R Controller is ideal for legacy-reduced server platforms. The WPCM450R interfaces with a host system via PCI interface to communicate with the Graphics core. It supports USB 2.0 and 1.1 for remote keyboard/mouse/ virtual media emulation. It also provides LPC interface to control Super IO functions. The WPCM450R is connected to the network via an external Ethernet PHY module. The BMC also supports two high-speed, 16550 compatible serial communication ports (UARTs). Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability and a processor interrupt system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which support higher speed modems. The WPCM450R communicates with onboard components via six SMBus interfaces, fan control, and Platform Environment Control Interface (PECI) buses. Note: For more information on IPMI configuration, please refer to the Embedded IPMI User's Guide posted on our Website @ http://www.supermicro.com/support/manuals/. 2-16 Chapter 3: Installation Chapter 3 Installation 3-1 Standardized Warning Statements The following statements are industry-standard warnings provided to warn the user of situations when potential bodily injury may occur. Should you have questions or experience difficulty, contact Supermicro's Technical Support department for assistance. Only certified technicians should attempt to install or configure components. Read this section in its entirety before installing or configuring components in the system. Battery Handling Warning! There is a danger of explosion if the battery is replaced incorrectly. Replace the battery only with the same or equivalent type recommended by the manufacturer. Dispose of used batteries according to the manufacturer's instructions. (Refer to Chapter 3 for more information on used battery disposal. Battery Handling (Japanese) Warnung Bei Einsetzen einer falschen Batterie besteht Explosionsgefahr. Ersetzen Sie die Batterie nur durch den gleichen oder vom Hersteller empfohlenen Batterietyp. Entsorgen Sie die benutzten Batterien nach den Anweisungen des Herstellers. ¡Advertencia! Existe peligro de explosión si la batería se reemplaza de manera incorrecta. Reemplazar la batería exclusivamente con el mismo tipo o el equivalente recomendado por el fabricante. Desechar las baterías gastadas según las instrucciones del fabricante. 3-1 X8OBN-F Platform User's Manual Attention Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer que par une pile de type semblable ou équivalent, recommandée par le fabricant. Jeter les piles usagées conformément aux instructions du fabricant. كيلعف ةحيحص ريغ ةقيرطب ةيراطبلا لادبتسا ةلاح يف راجفنا نم رطخ كانه ةيراطبلا لادبتسا ةعنصملا ةكرشلا هب تصوأ امك اهلداعي ام وأ عونلا سفنب طقف ةعناصلا ةكرشلا تاميلعتل اقفو ةلمعتسملا تايراطبلا نم صلخت Waarschuwing Er is ontploffingsgevaar indien de batterij verkeerd vervangen wordt. Vervang de batterij slechts met hetzelfde of een equivalent type die door de fabrikant aanbevolen wordt. Gebruikte batterijen dienen overeenkomstig fabrieksvoorschriften afgevoerd te worden. 3-2 Chapter 3: Installation Product Disposal Warning! Ultimate disposal of this product should be handled according to all national laws and regulations. Warnung Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen des Landes erfolgen. ¡Advertencia! Al deshacerse por completo de este producto debe seguir todas las leyes y reglamentos nacionales. Attention La mise au rebut ou le recyclage de ce produit sont généralement soumis à des lois et/ou directives de respect de l'environnement. Renseignez-vous auprès de l'organisme compétent. !אזהרה יש להחליף.קיימת סכנת פיצוץ של הסוללה במידה והוחלפה בדרך לא תקינה .את הסוללה בסוג התואם מחברת יצרן מומלצת .סילוק הסוללות המשומשות יש לבצע לפי הוראות היצרן نيناوقلا عيمجل اقفو هعم لماعتلا يغبني جتنملا اذه نم يئاهنلا صلختلا دنع ةينطولا حئاوللاو Waarschuwing De uiteindelijke verwijdering van dit product dient te geschieden in overeenstemming met alle nationale wetten en reglementen. 3-3 X8OBN-F Platform User's Manual 3-2 Static-Sensitive Devices Electrostatic Discharge (ESD) can damage electronic components. To avoid damaging your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from ESD. Precautions •Use a grounded wrist strap designed to prevent static discharge. •Touch a grounded metal object before removing the board from the antistatic bag. •Handle the board by its edges only; do not touch its components, peripheral chips, memory modules or gold contacts. •When handling chips or modules, avoid touching their pins. •Put the baseboard and peripherals back into their antistatic bags when not in use. •For grounding purpose, make sure that your system chassis provides excellent conductivity between the power supply, the case, the mounting fasteners and the baseboard. •Use only the correct type of onboard CMOS battery as specified by the manufacturer. Do not install the onboard battery upside down to avoid possible explosion. Unpacking The baseboard is shipped in antistatic packaging to avoid static damage. When unpacking the board, make sure the person handling it is static protected. Note: Please refer to the quick installation guide listed in Chapter 1 for more information on system installation. 3-4 Chapter 3: Installation 3-3 Populating the CPU Board Warning! When handling the processor, avoid placing direct pressure on the CPU pins, CPU socket, and the label area of the heatsink and the fan to avoid damaging the components and the system. Be sure to attach the CPU board to the CPU board plate before you install a component on the CPU board. 1. Always connect the power cord last, and always remove it before adding, removing or changing any hardware components. Make sure that you install the processor into the CPU socket before you install the CPU heatsink. 2. When purchasing a board without a 7500 Series processor pre-installed, make sure that the CPU socket plastic cap is in place, and none of the CPU socket pins are bent; otherwise, contact the retailer immediately. 3. Refer to our website at www.supermicro.com for CPU/Memory support updates. Installing a CPU on the CPU Board 1. Follow the instructions given in Chapter 1 to install the CPU board to the CPU board plate. 2. Press the socket clip to release the load plate, which covers the CPU socket, from its locking position. 3. Gently lift the socket clip to open the load plate. Warning: Shipment without the plastic cap properly installed will cause damage to the socket pins. 3-5 X8OBN-F Platform User's Manual Installing the CPU Heatsink on the CPU Board 1. If needed, apply the proper amount of thermal grease (with thickness of up to 0.13 mm) to the heatsink. (If you are using a heatsink purchased from SMC, please skip this step because the needed amount of the thermal grease has been applied to the heatsink.) 2. Place the heatsink on top of the CPU so that the two mounting holes on the heatsink are aligned with those on the retention mechanism. 3. Insert two push-pins on the sides of the heatsink through the mounting holes on the motherboard, and turn the push-pins clockwise to lock them. . Note: Reverse the steps indicated above to remove the heatsink from the CPU Board. 3-6 Chapter 3: Installation Installing Memory Modules on the CPU Board Notes: 1. Be sure to install the CPU board to the CPU board plate before installing any components to the CPU board. (See Chapter 1). 2. Check Supermicro's website for recommended memory modules. CAUTION Exercise extreme care when installing or removing DIMM modules to prevent any possible damage. X8OBN-CPU Rev.1.01 J47 J48 P2-DIMM6A P1-DIMM4A P2-DIMM5A P1-DIMM3A MB3 (for CPU2) MB4 (for CPU2) MB2 (for CPU1) CPU2 MB1 (for CPU1) P2-DIMM7A P1-DIMM1A P2-DIMM8A P1-DIMM2A P2-DIMM2A P1-DIMM8A P2-DIMM1A P1-DIMM7A MB1 (for CPU2) MB2 (for CPU2) CPU1 MB4 (for CPU1) P2-DIMM3A MB3 (for CPU1) P1-DIMM5A P1-DIMM6A P2-DIMM4A J35 J43 J44 J46 J45 J36 1. Insert the desired number of DIMMs into the memory slots, starting with P1DIMM #1A. (For best performance, please use the memory modules of the same type and the same speed in the same bank.) 2. Push the release tabs outwards on both ends of the DIMM slot to unlock it. 3. Align the key of the DIMM module with the receptive point on the memory slot. 4. Align the notches on both ends of the module with the receptive points on the ends of the slot. 5. Use two thumbs together to press the notches on both ends of the module straight down into the slot until the module snaps into place. 6. Press the release tabs to the lock positions to secure the DIMM module into the slot. Notches Press both notches straight down into the memory slot at the same time. Release Tabs Removing Memory Modules Reverse the steps above to remove the DIMM modules from the motherboard. 3-7 X8OBN-F Platform User's Manual 3-4 Installing the Baseboard into the Chassis Follow the instructions below to install the baseboard into the chassis. Tools Needed •Phillips Screwdriver •Pan_head #6 screws (23 pieces) •Standoffs (20 pieces, if needed) 1. Install the IO shield in the chassis. 2. Locate the mounting holes on the baseboard and the matching mounting holes on the chassis. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 Fan 10 Fan 9 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 CPU Board Slot 2 UID JPL1 LED6 LAN2 LAN1 Fan4 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot7 PCI-E 2.0 x8 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 JD1 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 BT1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 JPRST1 JPB1 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL I/O Hub 1 JPG1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JL1 JP21 T-SGPIO1 3. Place the baseboard in the chassis, making sure that the mounting holes on the baseboard match the corresponding mounting holes on the chassis. 4. Install standoffs in the chassis as needed. 5. Using the Phillips screwdriver, insert a Pan head #6 screw into mounting hole on the baseboard and its matching mounting hole on the chassis. Repeat this step to secure the baseboard to the chassis. 3-8 Chapter 3: Installation 3-5 Installing the Populated CPU Board on the Baseboard JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 CPU Slot4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 LAN1 LAN2 JP19 JP17 Fan 10 Fan 9 JPT1 JUID_OW1 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL CPU Slot2 Fan3 JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 CPU Board Slot 2 UID JPL1 LED6 CPU Slot3 Fan4 CPU Slot1 JP3 Fan7 Slot9 PCI-E 2.0 x8 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 BMC CTRL JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 JD1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA4 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 BT1 JBT1 JPRST1 JPB1 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 LED4 JL1 JP21 T-SGPIO1 Note: Be sure to install the CPU board to the CPU board plate before installing any components to the CPU board. (See Chapter 1.) After processors, memory modules and heatsinks are installed on the CPU board, and the baseboard is installed in the chassis, you can install the CPU board onto the baseboard. Follow the instructions below to install the CPU board onto the baseboard. 1. Locate the CPU_board slots on the X8OBN Baseboard. (Four CPU_board slots are available on the baseboard). 2. Align the pins on a CPU board against the receptive points of the CPU_board slot on the baseboard. Once they are aligned, press the CPU Board straight down to the baseboard until it is fully seated on the baseboard. Warning: To avoid damaging the CPU or CPU board, do not touch any components on the CPU board when installing it. Also be sure that the CPU board is fully seated on the CPU board slot. Install Populated CPU Board to BaseBoard X8OBN-CPU Rev.1.01 J47 J48 P2-DIMM6A P1-DIMM4A P2-DIMM5A P1-DIMM3A MB3 (for CPU2) MB4 (for CPU2) MB2 (for CPU1) CPU2 MB1 (for CPU1) P1-DIMM1A P2-DIMM7A P1-DIMM2A P2-DIMM8A P2-DIMM2A P1-DIMM8A P2-DIMM1A P1-DIMM7A MB1 (for CPU2) MB2 (for CPU2) CPU1 MB4 (for CPU1) MB3 (for CPU1) P2-DIMM3A P1-DIMM5A P2-DIMM4A P1-DIMM6A J35 J43 J44 J46 J45 CP UB oa rd Slo J36 CPU Board BaseBoard 3-9 t X8OBN-F Platform User's Manual 3-6 Installing the Bridge Card between the CPU Boards Once you've installed populated CPU boards on the baseboard, you can install the X8OBN-BRI Bridge card between the CPU boards. (If only one CPU board is installed on the baseboard, please skip this step.) Note: A Bridge card is needed to connect the pair(s) of the CPU boards installed on Slot1 & Slot2, and/or Slot3 & Slot4. There is no Bridge card needed between Slot2 and Slot3. Refer to the table below for details. CPU Board Installed on Slot1 CPU Board Installed on Slot2 CPU Board Installed on Slot3 CPU Board Installed on Slot4 X8OBN-BRI Bridge Card(s) to be Installed Yes Yes No No One card needed between Slot1 & Slot2 Yes Yes Yes Yes One card needed between Slot1 & Slot2; Another card needed between Slot3 & Slot4 X8OBN Bridge Card J1 J2 X8OBN-BR1 Rev. 1.01 J3 To connect to the CPU Board J4 X8OBN CPU Board Two Bridge Cards Four CPU Boards 3-10 Chapter 3: Installation 3-7 Memory Support for the X8OBN-F Platform Each X8OBN-F CPU Board supports up to 256 GB Registered ECC DDR3 1066 MHz memory in 16 DIMM slots. These RDIMMs run at 800/978/1066 via a memory buffer. X8OBN-CPU Rev.1.01 J47 J48 P2-DIMM6A P1-DIMM4A P2-DIMM5A P1-DIMM3A MB3 (for CPU2) MB4 (for CPU2) MB2 (for CPU1) CPU2 MB1 (for CPU1) P2-DIMM7A P1-DIMM1A P2-DIMM8A P1-DIMM2A P2-DIMM2A P1-DIMM8A P2-DIMM1A P1-DIMM7A MB1 (for CPU2) MB2 (for CPU2) CPU1 MB4 (for CPU1) P2-DIMM3A MB3 (for CPU1) P1-DIMM5A P1-DIMM6A P2-DIMM4A J35 J43 J46 J44 J45 J36 Processor & Memory Module Population Configuration For memory to work properly, follow the tables below for memory support. CPUs and the Corresponding Memory Modules (on Each CPU Board) CPU# Corresponding DIMM Modules CPU 1 P1-1A P1-2A P1-3A P1-4A P1-5A P1-6A P1-7A P1-8A CPU2 P2-1A P2-2A P2-3A P2-4A P2-5A P2-6A P2-7A P2-8A Processor and Memory Module Population on Each CPU Board Number of CPUs+DIMMs 2 CPUs & 8 DIMMs 2 CPUs & 10~16 DIMMs CPU and Memory Population Configuration Table (*For memory to work proper, please install DIMMs in pairs) CPU1 + CPU2 P1-1A/P1-3A/P1-5A/P1-7A, P2-1A/P2-3A/P2-5A/P2-7A CPU1/CPU2 P1-1A/P1-3A/P1-5A/P1-7A, P2-1A/P2-3A/P2-5A/P2-7A + Any memory pairs in P1, P2 DIMM slots Note 1: To optimize system performance, we recommend that 4-CPU or 8-CPU configuration be used in your system as shown in the table below. Please note that 1-CPU configuration has not been validated by SMC. Note 2: Due to a memory limitation posted by the Intel Hemisphere mode, please install only 32 or 64 DIMM modules in an 8-way system. 4-CPU or 8-CPU Configuration (-Recommended for Optimal System Performance) 4-CPU Configuration 2 CPUs per CPU Board Two CPU Boards Required: One on CPU_Board Slot1; Anther on CPU_Board Slot2 8-CPU Configuration 2 CPUs per CPU Board Four CPU Boards Required: Two CPU Boards on each CPU_Board Slot (from Slot1 to Slot4) 3-11 X8OBN-F Platform User's Manual RDIMM Support POR on the 7500 Series Processor Platform DIMM Slots per DDR Channel DIMMs Populated per DDR Channel RDIMM Type (RDIMM: Reg.= Registered) POR Speeds (in MHz) Ranks per DIMM (Any Combination) 1 1 Reg. ECC DDR3 800,978, 1066 SR, DR, or QR Note: Refer to the notes below for memory population instructions. Memory Capacity Maximum Memory Possible (8S) 4Gb DRAM Single Rank RDIMMs 512 GB (64 x 8GB DIMMs) Dual Rank RDIMMs 1024 GB (64 x 16GB DIMMs) Notes •Populate DIMMs starting with DIMM1A. •For the memory modules to work properly, please install DIMM modules in pairs (with even number of DIMMs installed). •All channels in a system will run at the fastest common frequency. 3-12 Chapter 3: Installation 3-8 Control Panel Connectors/I/O Ports The I/O ports are color coded in conformance with the PC 99 specification. See the picture below for the colors and locations of the various I/O ports. Back Panel Connectors/I/O Ports JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LAN CTRL 5 1 4 3 JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 2 JPWR3 Fan 10 Fan 9 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 J32 J25 CPU Board Slot 2 UID JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 7 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 JIPMB1 USB10 USB8 JWF1 JTPM1 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA4 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 Slot1 PCI-E 2.0 x8 in x16 6 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 JL1 JP21 T-SGPIO1 Back Panel I/O Port Locations and Definitions 1. Keyboard 2. Mouse 3. Back Panel USB Port 0 4. Back Panel USB Port 1 5. IPMI_Dedicated LAN 6. COM Port 1 (Turquoise) 7. VGA (Blue) 8. Gigabit LAN 1 9. Gigabit LAN 2 10.UID Switch 3-13 8 9 10 X8OBN-F Platform User's Manual ATX PS/2 Keyboard and PS/2 Mouse Ports PS/2 Keyboard/Mouse Pin Definitions The ATX PS/2 keyboard and PS/2 mouse are located next to the Back Panel USB Ports 0~1 on the baseboard. See the table at right for pin definitions. PS2 Keyboard PS2 Mouse Pin# Definition Pin# Definition 1 KB Data 1 Mouse Data 2 No Connection 2 No Connection 3 Ground 3 Ground 4 Mouse/KB VCC (+5V) 4 Mouse/KB VCC (+5V) 5 KB Clock 5 Mouse Clock 6 No Connection 6 No Connection VCC: with 1.5A PTC (current limit) JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 1. Keyboard JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 2. Mouse CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LAN CTRL JPWR4 Fan8 Slot10 PCI-E 2.0 x16 2 JP16 JPWR3 Fan 10 Fan 9 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 J32 J25 CPU Board Slot 2 UID JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 1 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPB1 LED4 PWR 1 I/O Hub 2 JPRST1 LED6 LAN2 LAN1 Fan4 JL1 JP21 T-SGPIO1 3-14 Chapter 3: Installation Universal Serial Bus (USB) Two Universal Serial Bus ports (USB 0/1) are located on the I/O back panel. Additionally, six Front Panel USB connections (USB 2/3, USB 4/5, USB 8, USB 10) are also on the baseboard to provide front chassis access. (Cables are not included). See the tables on the right for pin definitions. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 Pin# Definition 1 +5V 2 PO- 3 PO+ 4 Ground 5 NA CPU Board Slot 4 Fan12 VGA JP18 LAN1 LAN2 JPT1 JUID_OW1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JP16 JPWR4 JPWR3 Fan8 Slot10 PCI-E 2.0 x16 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 JD1 54 JIPMB1 USB10 USB8 JWF1 3 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 6 USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 ICH10R JPME2 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 BT1 JBT1 Slot3 PCI-E 2.0 x8 T-SGPIO2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 JPB1 2 1 JPG1 BMC CTRL PWR 1 I/O Hub 2 LED4 1 +5V PO- 2 PO- 3 PO+ 3 PO+ 4 Ground 4 Ground 5 NC 5 Key (NC= No connection) 6. Front Panel USB 10 Fan3 CPU Board Slot 1 +5V 2 5. Front Panel USB 8 JP19 JP17 LAN CTRL JPRST1 LED6 JPL1 J32 J25 CPU Board Slot 2 UID 1 4. Front Panel USB 4/5 CPU Board Slot 3 Fan4 Fan 10 Fan 9 USB 3/5 Pin # Definition 3. Front Panel USB 2/3 Fan5 J29 Fan 11 USB 2/4/8/10 Pin # Definition 2. Backpanel USB 1 Fan6 J30 FP USB (2/3, 4/5) Pin Definitions 1. Backpanel USB 0 JF1 Rev. 1.01 IPMI LAN COM1 FP CRTL Backplane USB (0/1) Pin Definitions JL1 JP21 T-SGPIO1 3-15 X8OBN-F Platform User's Manual Serial Ports COM1 Two COM connections (COM1 & COM2) are located on the motherboard. COM1 is located on the Backplane I/O panel. COM2 are located next to SATA Ports 0/1 to provides front accessible serial support. See the table on the right for pin definitions. 1 Serial COM) Ports Pin Definitions Pin # Definition Pin # Definition 1 DCD 6 DSR 2 RXD 7 RTS 3 TXD 8 CTS 4 DTR 9 RI 5 Ground 10 N/A COM1 COM2 2 COM2 Video Connection A Video (VGA) port is located next to COM1 on the I/O backplane. Refer to the board layout below for the location. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 1. COM1 JF1 2. COM2 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 3. VGA Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP17 Fan3 CPU Board Slot 1 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 JP19 JPT1 JUID_OW1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 UID JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 1 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 JD1 JPME1 JPME2 ICH10R Slot1 PCI-E 2.0 x8 in x16 USB4/5 USB2/3 Slot2 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 2 COM2 PWR 2 BT1 JBT1 Slot3 PCI-E 2.0 x8 T-SGPIO2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 Fan1 BMC CTRL JPB1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPRST1 LED6 LAN2 LAN1 Fan4 CPU Board Slot 2 Fan 10 Fan 9 JL1 JP21 T-SGPIO1 3-16 3 Chapter 3: Installation Ethernet Ports LAN Ports Pin Definition Two Ethernet ports (LAN1/LAN2) are located on the I/O backplane on the Pin# Definition baseboard. In addition, an IPMI_Dedicated LAN is located above USB 0/1 ports on the backplane to provide KVM support for IPMI 2.0. All these ports accept RJ45 type cables. Note: Please refer to the LED Indicator Section for LAN LED information. 1 P2V5SB 10 SGND 2 TD0+ 11 Act LED 3 TD0- 12 P3V3SB 4 TD1+ 13 Link 100 LED (Yellow, +3V3SB) 5 TD1- 14 Link 1000 LED (Yellow, +3V3SB) 6 TD2+ 15 Ground 7 TD2- 16 Ground 8 TD3+ 17 Ground 9 TD3- 18 Ground (NC: No Connection) JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 1. LAN1 JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 2. LAN2 CPU Board Slot 4 Fan12 3. IPMI_LAN Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP17 CPU Board Slot 1 LAN CTRL 3 Fan3 JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 JP19 JPT1 JUID_OW1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 UID JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 Slot1 PCI-E 2.0 x8 in x16 1 JPWR2 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPB1 LED4 PWR 1 I/O Hub 2 JPRST1 LED6 LAN2 LAN1 Fan4 CPU Board Slot 2 Fan 10 Fan 9 JL1 JP21 T-SGPIO1 3-17 2 X8OBN-F Platform User's Manual Unit Identifier Switch UID Switch A Unit Identifier (UID) switch and two LED Indicators are located on the X8OBN-F baseboard. The UID switch is located next to the LAN ports on the backplane. The Rear UID LED (LED6) is located next to the UID switch. The Front Panel UID LED is located at Pins 7/8 of the Front Control Panel at JF1. Connect a cable to Pins 7/8 on JF1 for Front Panel UID LED indication. When you press the UID switch, both Rear UID LED and Front Panel UID LED Indicators will be turned on. Press the UID switch again to turn off both LED Indicators. These UID Indicators provide easy identification of a system unit that may be in need of service. Pin# Definition 1 Ground 2 Ground 3 Button In 4 Ground UID LED (LE2) Status Color/State OS Status Blue: On Windows OS Unit Identified Blue: Blinking Linux OS Unit Identified Note: UID can also be triggered via IPMI on the baseboard. For more information on IPMI, please refer to the IPMI User's Guide posted on our Website @http://www.supermicro.com. 1. UID Switch 2. Rear UID LED (LED6) 3. Front UID LED KB/Mouse USB 0/1 FP CRTL JF1 Fan6 Rev. 1.01 IPMI LAN COM1 1 JWD1 JOH1 X8OBN-F Baseboard CPU Board Slot 4 20 Fan12 Fan 11 VGA X Slot10 PCI-E 2.0 x16 3 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot7 PCI-E 2.0 x8 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JD1 JPME2 ICH10R USB4/5 USB2/3 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 NIC2 Link LED NIC2 Activity LED Red+ (Blue LED Cathode) 3.3V JPWR2 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 NIC1 Activity LED Power Fail LED BT1 JBT1 Slot3 PCI-E 2.0 x8 Slot1 PCI-E 2.0 x8 in x16 3 NIC1 Link LED Blue+ (OH/Fan Fail/ PWR FaiL/UID LED) PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL I/O Hub 1 JPG1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 ID_UID_SW/3/3V Stby HDD LED JP16 JPWR4 Fan8 JPWR3 J32 J25 JP17 Fan3 CPU Board Slot 1 X 3.3 V FP PWRLED JP19 JPT1 JUID_OW1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 Fan 10 Fan 9 LAN CTRL JPB1 LED6 LAN2 LAN1 Fan4 CPU Board Slot 2 UID NMI CPU Board Slot 3 JP18 JPRST1 2 19 Ground Fan5 J30 J29 1 Ground Reset Reset Button Ground PWR Power Button 2 JL1 JP21 T-SGPIO1 3-18 1 Chapter 3: Installation Front Control Panel JF1 contains header pins for various buttons and indicators that are normally located on a control panel at the front of the chassis. These connectors are designed specifically for use with Supermicro's server chassis. See the figure below for the descriptions of the various control panel buttons and LED indicators. Refer to the following section for descriptions and pin definitions. JF1 Header Pins JWD1 JOH1 KB/Mouse X8OBN-F Baseboard JF1 Fan6 IPMI LAN USB 0/1 COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 Fan 10 Fan 9 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 J32 J25 CPU Board Slot 2 UID JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 I-SATA2 I-SATA0 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 JL1 JP21 T-SGPIO1 20 19 Ground NMI X X 3.3 V FP PWRLED ID_UID_SW/3/3V Stby HDD LED NIC1 Link LED NIC1 Activity LED NIC2 Link LED NIC2 Activity LED Blue+ (OH/Fan Fail/ PWR FaiL/UID LED) Red+ (Blue LED Cathode) Power Fail LED 3.3V Ground Ground 2 3-19 1 Reset Reset Button PWR Power Button X8OBN-F Platform User's Manual Front Control Panel Pin Definitions NMI Button NMI Button Pin Definitions (JF1) The non-maskable interrupt button header is located on pins 19 and 20 of JF1. Refer to the table on the right for pin definitions. Pin# Definition 19 Control 20 Ground Power LED Power LED Pin Definitions (JF1) The Power LED connection is located on pins 15 and 16 of JF1. Refer to the table on the right for pin definitions. Pin# Definition 15 3.3V 16 PWR LED A. NMI B. PWR LED JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 JF1 20 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 19 Ground CPU Board Slot 4 Fan12 NMI A Fan5 J30 X J29 Fan 11 VGA CPU Board Slot 3 X JP18 LAN1 LAN2 JPT1 JUID_OW1 JP16 JPWR4 JPWR3 Fan8 Slot10 PCI-E 2.0 x16 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 PLX PCI Bridge Battery NIC2 Link LED NIC2 Activity LED Blue+ (OH/Fan Fail/ PWR FaiL/UID LED) JD1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 Red+ (Blue LED Cathode) 3.3V JPWR2 BT1 JBT1 Slot1 PCI-E 2.0 x8 in x16 NIC1 Activity LED PWR 2 Slot4 PCI-E 2.0 x16 NIC1 Link LED Power Fail LED JP22 T-SGPIO2 BMC CTRL JPB1 LED4 PWR 1 I/O Hub 2 ID_UID_SW/3/3V Stby HDD LED Fan3 CPU Board Slot 1 LAN CTRL 3.3 V JP19 JP17 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 UID J32 J25 CPU Board Slot 2 Fan 10 Fan 9 JPRST1 LED6 B FP PWRLED Fan4 Ground Reset Reset Button Ground PWR Power Button 2 JL1 JP21 T-SGPIO1 3-20 1 Chapter 3: Installation HDD LED HDD LED Pin Definitions (JF1) The HDD LED connection is located on pins 13 and 14 of JF1. Attach a cable here to indicate HDD activity. See the table on the right for pin definitions. Pin# Definition 13 3.3V Standby 14 HD Active NIC1/NIC2 LED Indicators GLAN1/2 LED Pin Definitions (JF1) The NIC (Network Interface Controller) LED connection for GLAN port 1 is located on pins 11 and 12 of JF1, and the LED connection for GLAN Port 2 is on Pins 9 and 10. Attach the NIC LED cables to display network activity. Refer to the table on the right for pin definitions. Pin# Definition 9 NIC 2 Activity LED 10 NIC 2 Link LED 11 NIC 1 Activity LED 12 NIC 1 Link LED A. HDD LED B. NIC1 Link LED C. NIC1 Activity LED D. NIC2 Link LED E. NIC2 Activity LED JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 JF1 20 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 19 Ground CPU Board Slot 4 Fan12 NMI Fan5 J30 X J29 Fan 11 VGA CPU Board Slot 3 X JP18 LAN1 LAN2 JP19 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 PLX PCI Bridge Battery C D NIC2 Activity LED E NIC2 Link LED Blue+ (OH/Fan Fail/ PWR FaiL/UID LED) JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 PWR 2 JD1 JPME2 ICH10R Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 Red+ (Blue LED Cathode) 3.3V JPWR2 Slot3 PCI-E 2.0 x8 Slot1 PCI-E 2.0 x8 in x16 NIC1 Activity LED BT1 JBT1 USB4/5 USB2/3 JPB1 Slot4 PCI-E 2.0 x16 ID_UID_SW/3/3V Stby B NIC1 Link LED Power Fail LED JP22 T-SGPIO2 BMC CTRL PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 LED4 AHDD LED JP17 JPT1 JUID_OW1 JPWR3 Fan 10 Fan 9 JPRST1 LED6 JPL1 J32 J25 CPU Board Slot 2 UID 3.3 V FP PWRLED Fan4 Ground Reset Reset Button Ground PWR Power Button 2 JL1 JP21 T-SGPIO1 3-21 1 X8OBN-F Platform User's Manual Overheat (OH)/Fan Fail/PWR Fail/ UID LED OH/Fan Fail/PWR Fail/UID LED Pin Definitions (JF1) Pin# Connect an LED cable to OH/Fan Fail/ FP UID connection on pins 7 and 8 of JF1 to provide advanced warnings of chassis overheat or fan failure. It also works as the front panel UID LED indicator. The Red LED takes precedence over the Blue LED by default. Refer to the table on the right for pin definitions. Definition 7 Red+ (Blue LED Cathode) 8 Blue+ (OH/Fan Fail/PWR Fail/ UID LED) OH/Fan Fail Indicator Status State Definition Off Normal On Overheat Flashing Fan Fail Power Fail LED PWR Fail LED Pin Definitions (JF1) The Power Fail LED connection is located on pins 5 and 6 of JF1. Refer to the table on the right for pin definitions. Pin# Definition 5 3.3V 6 PWR Supply Fail A. Front UID LED (Blue) B. OH/ Fail/PWR Fail LED (Red) C. PWR Supply Fail JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 JF1 20 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 19 Ground CPU Board Slot 4 Fan12 NMI Fan5 J30 X J29 Fan 11 VGA CPU Board Slot 3 X JP18 LAN1 LAN2 JP19 JP17 JPT1 JUID_OW1 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery NIC1 Activity LED NIC2 Link LED NIC2 Activity LED Blue+ (OH/Fan Fail/ PWR FaiL/UID LED) JD1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 JIPMB1 USB10 USB8 JWF1 CPower Fail LED JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 3.3V Ground Reset Reset Button Ground PWR Power Button 2 JL1 JP21 T-SGPIO1 3-22 A Red+ (Blue LED Cathode) JPWR2 BT1 JBT1 Slot1 PCI-E 2.0 x8 in x16 B NIC1 Link LED PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPB1 LED4 PWR 1 I/O Hub 2 ID_UID_SW/3/3V Stby HDD LED Fan3 JPWR3 Fan 10 Fan 9 JPRST1 LED6 JPL1 J32 J25 CPU Board Slot 2 UID 3.3 V FP PWRLED Fan4 1 Chapter 3: Installation Reset Button Reset Button Pin Definitions (JF1) The Reset Button connection is located on pins 3 and 4 of JF1. Attach it to a hardware reset switch on the computer case. Refer to the table on the right for pin definitions. Pin# Definition 3 Reset 4 Ground Power Button Power Button Pin Definitions (JF1) The Power Button connection is located on pins 1 and 2 of JF1. Momentarily contacting both pins will power on/off the system. This button can also be configured to function as a suspend button (with a setting in BIOS - See Chapter 5). To turn off the power when the system is set to suspend mode, press the button for at least 4 seconds. Refer to the table on the right for pin definitions. Pin# Definition 1 Signal 2 Ground A. Reset Button B. PWR Button JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 JF1 20 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 19 Ground CPU Board Slot 4 Fan12 NMI Fan5 J30 X J29 Fan 11 VGA CPU Board Slot 3 X JP18 LAN1 LAN2 JP19 JP17 JPT1 JUID_OW1 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 PLX PCI Bridge Battery NIC2 Link LED NIC2 Activity LED Blue+ (OH/Fan Fail/ PWR FaiL/UID LED) JD1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 Red+ (Blue LED Cathode) 3.3V JPWR2 BT1 JBT1 Slot1 PCI-E 2.0 x8 in x16 NIC1 Activity LED PWR 2 Slot4 PCI-E 2.0 x16 NIC1 Link LED Power Fail LED JP22 T-SGPIO2 BMC CTRL JPB1 LED4 PWR 1 I/O Hub 2 ID_UID_SW/3/3V Stby HDD LED Fan3 JPWR3 Fan 10 Fan 9 JPRST1 LED6 JPL1 J32 J25 CPU Board Slot 2 UID 3.3 V FP PWRLED Fan4 Ground Reset Reset Button A Ground PWR Power Button B 2 JL1 JP21 T-SGPIO1 3-23 1 X8OBN-F Platform User's Manual 3-9 Connecting Cables GPU 8-pin PWR Connector Pin Definitions Power Connectors Two main power supply connectors (JP21/ Pins JP22), four GPU 8-pin power connectors (JPWR1/JPWR2/JPWR3/JPWR4), and four HDD power connectors (JP16~JP19) are located on the X8OBN Baseboard. These power connectors meet the SSI EPS 12V specification. These power connectors must be connected to your power supply to provide adequate power to your system and components. Failure to do so will void the manufacturer warranty on your power supply and the system. See the table on the right for pin definitions. 1~3 +12V 4~8 GND Definition (GPU PWR cable req'd for graphics cards) HDD 8-pin PWR Connector Pin Definitions Pins Definition 1~4 GND 5/6 +12V 7/8 +5V (HDD PWR cable required for HDDs) DOM Power Connector DOM PWR Pin Definitions A power connector for SATA DOM (Disk_On_ Module) Devices is located at JWF1. Connect the appropriate cable here to provide power support for your DOM devices. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard Definition 1 +5V 2 Ground 3 Ground JF1 Fan6 Rev. 1.01 IPMI LAN USB 0/1 COM1 FP CRTL Pin# A. CPU Board Slot 4 Fan12 Fan5 J30 B. J29 Fan 11 VGA CPU Board Slot 3 JP18 Fan3 E F CPU Board Slot 1 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JP16 JPWR3 J32 J25 JPT1 JUID_OW1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 Fan 10 Fan 9 JP19 JP17 LAN CTRL Slot8 PCI-E 2.0 x16 I/O Hub 1 J26 PLX PCI Bridge Battery JIPMB1 USB10 USB8 G JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 COM2 I-SATA2 I-SATA0 3-24 Fan1 USB4/5 USB2/3 Slot2 PCI-E 2.0 x8 in x16 T-SGPIO2 ICH10R JPME2 JPME1 JL1 JP21 T-SGPIO1 PWR 2 JD1 Slot3 PCI-E 2.0 x8 J K I H PWR 2 (JP21) (Req'd) C. JPWR1: 8-pin Processor PWR (Req'd) D. JPWR2: 8-pin Processor PWR (Req'd) sor PWR (Req'd) F. JPWR4: 8-pin ProcesG. JPWF1: SATA Device JPWR2 PWR (Req'd for SATA BT1 JBT1 Slot1 PCI-E 2.0 x8 in x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 Slot4 PCI-E 2.0 x16 (JP22) sor PWR (Req'd) CD Slot6 PCI-E 2.0 x16 JPRST1 A Slot7 PCI-E 2.0 x8 JPG1 BMC CTRL PWR 1 I/O Hub 2 LED4 1 E. JPWR3: 8-pin Proces- JP3 Fan7 Slot9 PCI-E 2.0 x8 JPB1 LED6 LAN2 LAN1 Fan4 CPU Board Slot 2 UID PWR (Req'd) B devices) H/I/J/K: HDD PWR Chapter 3: Installation Fan Headers Fan Headers The X8OBN Baseboard has six system fan headers and four CPU_card fan Fan Type headers. All these are 4-pin fans and are backward_compatible with the traditional 3-pin fans. In addition, two 3-pin IOH fan headers are located at Fan1 and Fan2. Fan speed control is available for 4-pin fans only*. See the tables on the right for more information. (*Fan speed control is available via Hardware Health Monitoring in the Advanced BIOS Section for 4-pin fans only.) # of Pins Q'ty Fan No. IOH Fans 3-pin Fan 2 Fan7 (IOH1)/ Fan8 (IOH2) CPU_ Board Fans 4-pin Fan 4 Fans 3~6 System Fans 4-pin Fan 6 Fan1/Fan2, Fans 9~12 Fan Header Pin Definitions Pin# Definition 1 Ground 2 +12V 3 Tachometer 4 PWR Modulation (4-pin fans only) Chassis Intrusion A Chassis Intrusion header is located at JL1 on the baseboard. Attach an appropriate cable from the chassis to inform you of possible chassis intrusion when the chassis is opened. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard FP CRTL Fan12 J30 J29 Intrusion Input 2 Ground Fan6 F L K Fan5 E Fan4 D CPU Board Slot 3 LAN2 JP17 I JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL B JPWR4 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JD1 JPME2 ICH10R Slot2 PCI-E 2.0 x8 in x16 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 G Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-25 COM2 Fan1 JPME1 F. Fan6 (CPU Slot4) G. Fan1 (System Fan) I/J. Fans 9/10 (System JPWR2 Slot3 PCI-E 2.0 x8 C. Fan3 (CPU Slot1) H. Fan2 (System Fan) JP22 BT1 JBT1 USB4/5 USB2/3 JPRST1 JPB1 Slot4 PCI-E 2.0 x16 H JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL B. Fan8 Fan (IOH2) E. Fan5 (CPU Slot3) PWR 1 I/O Hub 2 A. Fan7 (IOH1) D. Fan4 (CPU Slot2) A JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot8 PCI-E 2.0 x16 C JP16 Fan8 Slot10 PCI-E 2.0 x16 LED4 JP18 JP19 J PWR 2 Fan 10 Fan 9 JPWR3 J32 J25 CPU Board Slot 2 UID JPL1 LED6 Definition 1 CPU Board Slot 4 LAN1 VGA Fan 11 Pin# JF1 Rev. 1.01 IPMI LAN USB 0/1 COM1 Chassis Intrusion Pin Definitions M JL1 JP21 T-SGPIO1 Fans) K/L. Fans 11/12 (System Fans) M. Chassis Intrusion X8OBN-F Platform User's Manual Internal Buzzer Internal Buzzer Pin Definition The Internal Speaker, located at SP1, can be used to provide audible indica- Pin# tions for various beep codes. See the table on the right for pin definitions. Refer to the layout below for the location of the Internal Buzzer. Definitions Pin 1 Pos. (+) Beep In Pin 2 Neg. (-) Alarm Speaker Power LED/Speaker PWR LED Connector Pin Definitions On the JD1 header, pins 1-3 are used for power LED indication, and pins 4-7 are for the speaker. See the tables on the right for pin definitions. Please note that the speaker connector pins (4-7) are for use with an external speaker. If you wish to use the onboard speaker, close pins 6-7 with a cap. KB/Mouse Definition Pin 1 Anode (+) Pin2 Cathode (-) Pin3 NA Speaker Connector Pin Settings Pin Setting JWD1 JOH1 X8OBN-F Baseboard Definition Pins 4-7 External Speaker Pins 6-7 Internal Speaker FP CRTL JF1 Fan6 Rev. 1.01 IPMI LAN USB 0/1 COM1 Pin Setting CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 Fan 10 Fan 9 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 A. Internal Buzzer JPWR3 J32 J25 CPU Board Slot 2 UID JPL1 B. PWR LED/Speaker JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-26 A COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 B JL1 JP21 T-SGPIO1 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 Chapter 3: Installation TPM Header/Port 80 TPM/Port 80 Header Pin Definitions A Trusted Platform Module/Port 80 header is located at JTPM1 to provide TPM and Port 80 support, which will enhance system performance and data security. See the table on the right for pin definitions. Pin # Definition 2 GND 3 LFRAME# 4 <(KEY)> 5 LRESET# 6 +5V (X) 7 LAD 3 8 LAD 2 9 +3.3V 10 LAD1 11 LAD0 12 GND 13 SMB_CLK4 14 SMB_DAT4 15 +3V_DUAL 16 SERIRQ 17 GND 18 CLKRUN# (X) 19 LPCPD# 20 LDRQ# (X) Overheat LED Pin Definitions The JOH1 header is used to connect an LED indicator to provide warnings of chassis overheating or fan failure. This LED will blink when a fan failure occurs. Refer to the table on right for pin definitions. KB/Mouse Pin# Definition 1 5vDC 2 OH Active OH/Fan Fail LED Status JWD1 JOH1 X8OBN-F Baseboard FP CRTL B Rev. 1.01 IPMI LAN USB 0/1 Definition LCLK Overheat LED/Fan Fail COM1 Pin # 1 State Message Solid Overheat Blinking Fan Fail JF1 Fan6 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 Fan 10 Fan 9 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 A. TPM/Port 80 Head- JPWR3 J32 J25 CPU Board Slot 2 UID JPL1 er JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 A JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-27 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 JL1 JP21 T-SGPIO1 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 B. Overheat LED X8OBN-F Platform User's Manual T-SGPIO 1/2 Headers T-SGPIO Pin Definitions Two SGPIO (Serial-Link General Purpose Input/Output) headers are located on the baseboard. These headers support Serial_Link interface for onboard SATA connections. See the table on the right for pin definitions. KB/Mouse Definition Pin Definition 1 NC 2 NC 3 Ground 4 Data 5 Load 6 Ground 7 Clock 8 NC Note: NC= No Connection JWD1 JOH1 X8OBN-F Baseboard FP CRTL JF1 Fan6 Rev. 1.01 IPMI LAN USB 0/1 COM1 Pin# CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 Fan 10 Fan 9 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 A. T-SGPIO1 JPWR3 J32 J25 CPU Board Slot 2 UID JPL1 B. T-SGPIO2 JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-28 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 B A JL1 JP21 T-SGPIO1 Chapter 3: Installation 3-10 Jumper Settings Explanation of Jumpers Connector Pins To modify the operation of the baseboard, jumpers can be used to choose between optional settings. Jumpers create shorts between two pins to change the function of the connector. Pin 1 is identified with a square solder pad on the printed circuit board. See the baseboard layout pages for jumper locations. Setting GLAN Enable/Disable JWD1 JOH1 KB/Mouse IPMI LAN USB 0/1 COM1 Disabled FP CRTL A. GLAN Ports Enable JF1 CPU Board Slot 4 Fan5 J30 J29 VGA CPU Board Slot 3 JP18 CPU Board Slot 2 JP17 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 JP19 JPT1 JUID_OW1 JP16 JPWR4 Fan8 JPWR3 J32 J25 JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-29 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 JL1 JP21 T-SGPIO1 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPB1 LED4 PWR 1 I/O Hub 2 JPRST1 LED6 LAN2 LAN1 Fan4 Slot8 PCI-E 2.0 x16 Pin 1-2 short Enabled (default) Fan6 Slot10 PCI-E 2.0 x16 1 2-3 Rev. 1.01 LAN CTRL 2 1-2 Fan12 A 3 Jumper Setting Definition X8OBN-F Baseboard Fan 10 Fan 9 1 GLAN Enable Jumper Settings JPL1 enables or disables the GLAN Port1/GLAN Port2 on the baseboard. See the table on the right for jumper settings. The default setting is Enabled. UID 2 Jumper Cap Note: On two pin jumpers, "Closed" means the jumper is on, and "Open" means the jumper is off the pins. Fan 11 3 X8OBN-F Platform User's Manual CMOS Clear JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads to prevent the accidental clearing of CMOS. To clear CMOS, use a metal object such as a small screwdriver to touch both pads at the same time to short the connection. Always remove the AC power cord from the system before clearing CMOS. Note 1. For an ATX power supply, you must completely shut down the system, remove the AC power cord, and then short JBT1 to clear CMOS. Note 2. Be sure to remove the onboard CMOS Battery before you short JBT1 to clear CMOS. Note 3. Clearing CMOS will also clear any passwords. Watch Dog Enable/Disable Watch Dog Jumper Settings Watch Dog (JWD1) is a system monitor that can reboot the system when a software application hangs. Close Pins 1-2 to reset the system if an application hangs. Close Pins 2-3 to generate a non-maskable interrupt signal for the application that hangs. See the table on the right for jumper settings. Watch Dog must also be enabled in the BIOS. Jumper Setting Reset (default) Pins 2-3 NMI Open Disabled B JWD1 JOH1 KB/Mouse X8OBN-F Baseboard A. Clear CMOS JF1 B. Watch Dog Enable Fan6 Rev. 1.01 IPMI LAN USB 0/1 COM1 FP CRTL CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 Fan 10 Fan 9 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 CPU Board Slot 2 JPL1 JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 Battery JPME1 JD1 ICH10R USB4/5 USB2/3 Slot2 PCI-E 2.0 x8 in x16 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JPWR2 BT1 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-30 COM2 Fan1 A JBT1 Slot3 PCI-E 2.0 x8 JL1 JP21 T-SGPIO1 PWR 2 PLX PCI Bridge JPME2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 UID Definition Pins 1-2 Chapter 3: Installation VGA Enable VGA Enable Jumper Settings Jumper JPG1 allows the user to enable the onboard VGA connector. The default Jumper Setting setting is 1-2 to enable the connection. See the table on the right for jumper settings. Definition 1-2 Enabled (Default) 2-3 Disabled TPM Support Enable TPM Support Enable Jumper Settings JPT1 allows the user to enable TPM (Trusted Platform Modules) support which will enhance data integrity and system security. See the table on the right for jumper settings. The default setting is enabled. Jumper Setting Definition 1-2 Enabled 2-3 Disabled Note: For more information on IPMI configuration, please refer to the WPCM 450 IPMI BMC User's Guide posted on our Website @ http://www. supermicro.com. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard JF1 Fan6 IPMI LAN USB 0/1 COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 Fan 10 Fan 9 JP19 B JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 A. VGA Enabled JPWR3 J32 J25 CPU Board Slot 2 UID JPL1 B. TPM Enabled JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 A J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-31 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 JL1 JP21 T-SGPIO1 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 JPG1 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 X8OBN-F Platform User's Manual BMC Enable BMC Enable Jumper Settings Jumper JPB1 allows you to enable the embedded BMC (Baseboard Manage- Jumper Setting ment) Controller to provide IPMI 2.O/ KVM support on the motherboard. See the table on the right for jumper settings. BMC Enable Pins 2-3 Normal (Default) ME Recovery ME Recovery Select Jumper Settings Close Jumper JPME1 to use ME Firmware Recovery mode, which will limit system resource for essential functionality use only without putting restrictions on power use. In single operation mode, online upgrade will be available via Recovery mode. See the table on the right for jumper settings. KB/Mouse Definition Open Normal (Default) Closed Manufacture Mode FP CRTL JF1 Fan6 Rev. 1.01 IPMI LAN USB 0/1 COM1 Jumper Setting JWD1 JOH1 X8OBN-F Baseboard Definition Pins 1-2 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 CPU Board Slot 2 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 Fan 10 Fan 9 J32 J25 UID JPL1 A. BMC Enabled JP3 Fan7 Slot9 PCI-E 2.0 x8 B. ME Mode Se- Slot8 PCI-E 2.0 x16 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-32 COM2 JL1 JP21 T-SGPIO1 PWR 2 JD1 ICH10R Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 Slot1 PCI-E 2.0 x8 in x16 JPWR2 BT1 B JBT1 Slot3 PCI-E 2.0 x8 JPME2 Slot4 PCI-E 2.0 x16 USB4/5 USB2/3 A JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 JPB1 LED6 LAN2 LAN1 Fan4 lect Chapter 3: Installation Manufacturer Mode Select ME Mode Select Jumper Settings Close this jumper (JPME2) to bypass SPI flash security and force the system to use the Manu- Jumper Setting facturer Mode which will allow you to flash the system firmware from a host server to modify system settings. See the table on the right for jumper settings. Normal (Default) Closed Manufacture Mode JUID_OW1 (UID_Overwriting) When the jumper JUID_OW1 is set to Off (default), the Red LED (Overheat/Fan Fail/PWR Fail/UID LED) located on Pin 8 of the Front Control Panel (JF1) will take precedence over the Blue UID_LED located on Pin 7 of JF1. In this case, when the Red LED is on, the Blue LED will be turned off. When the RED LED is off, the Blue UID_LED can be on or off. In other words, the Red LED signal overwrites the Blue UID_LED signal if J_UID-OW is set to off. When the jumper J_UID_OW is On, the Red LED (OH/Fan Fail/PWR Fail/UID LED) and the Blue_UID_LED work independently. The Red LED will have no effects on the Blue LED. See the table on the right for jumper settings. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 Fan12 Fan5 J30 J29 VGA CPU Board Slot 3 JP18 B Fan3 CPU Board Slot 1 JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 JP19 JP17 JPT1 JUID_OW1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 Fan 10 Fan 9 LAN CTRL JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 PWR 2 JD1 A Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 ICH10R JPME2 JPME1 Slot2 PCI-E 2.0 x8 in x16 Slot1 PCI-E 2.0 x8 in x16 JPWR2 BT1 JBT1 Slot3 PCI-E 2.0 x8 USB4/5 USB2/3 JPRST1 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 LED4 JPB1 LED6 LAN2 LAN1 Fan4 CPU Board Slot 2 UID Jumper Off (Default) Definition Red OH/Fan Fail/PWR Fail LED (Pin 8 of JF1) takes precedence over (overwrites) the Blue UID_LED (Pin 7 of JF1). Red LED: On, Blue LED: Off, Red LED: Off, Blue LED: On or Off On Red LED (OH/Fan Fail/PWR Fail LED) and the Blue UID_ LED function independently. Red LED does not overwrite the Blue LED. The Red LED has no effects on the Blue_UID LED Red LED: On, Blue LED: On,Off Red LED: Off, Blue LED: On, Off B. JUID_OW1 CPU Board Slot 4 Fan 11 UID_Overwriting Jumper Settings A. JPME2 JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 Definition Open JL1 JP21 T-SGPIO1 3-33 X8OBN-F Platform User's Manual BMC Reset Use Jumper JPRST1 to reset the BMC settings on the motherboard. See the table on the right for jumper settings. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 Fan12 Fan5 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP17 Fan3 CPU Board Slot 1 JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 JP19 JPT1 JUID_OW1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 Fan 10 Fan 9 LAN CTRL JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 Battery JPWR2 JD1 ICH10R JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 PWR 2 BT1 JBT1 Slot3 PCI-E 2.0 x8 Slot1 PCI-E 2.0 x8 in x16 JP22 JPWR1 Fan2 PLX PCI Bridge JPME2 A Slot4 PCI-E 2.0 x16 USB4/5 USB2/3 JPRST1 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 LED4 JPB1 LED6 LAN2 LAN1 Fan4 CPU Board Slot 2 UID Definition Closed BMC Reset Closed Normal (Default) able CPU Board Slot 4 J30 Jumper Setting A. BMC Reset En- JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 BMC Reset Jumper Settings JL1 JP21 T-SGPIO1 3-34 Chapter 3: Installation 3-11 Onboard LED Indicators Activity LED Link LED GLAN LEDs Rear View (when facing the rear side of the chassis) Two LAN ports (LAN 1/LAN 2) are located on the I/O Backplane of the baseboard. Each Ethernet LAN port has two LEDs. The yellow LED indicates activity, while the other Link LED may be green, amber or off to indicate the speed of the connections. See the tables at right for more information. LAN 1/LAN 2 Link LED (Right) LED State LED Color Definition Off No Connection or 10 Mbps Green 100 Mbps Amber 1 Gbps LAN 1/LAN 2 Activity LED (Left) LED State Color Status Definition Yellow Flashing Active LAN 1/LAN 2 IPMI Dedicated LAN LEDs IPMI LAN (F models only) Link LED In addition to LAN 1/LAN 2, an IPMI Dedicated LAN is also located on the I/O Backplane of the baseboard. The amber LED on the right indicates activity, while the green LED on the left indicates the speed of the connection. See the tables at right for more information. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard USB 0/1 IPMI LAN (X8ST3-F) Color/State IPMI LAN Link LED (Left) & Activity LED (Right) Green: Solid 100 Mbps Activity (Right) Amber: Blinking Active B. IPMI LAN LEDs CPU Board Slot 4 Fan12 Definition Link (Left) A. LAN1/2 LEDs JF1 Fan6 IPMI LAN COM1 FP CRTL Rev. 1.01 Activity LED Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 J32 J25 Fan 10 Fan 9 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 UID JP3 Fan7 Slot9 PCI-E 2.0 x8 B I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JD1 Slot2 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 COM2 Fan1 JPME2 ICH10R PWR 2 BT1 JBT1 JPME1 Slot1 PCI-E 2.0 x8 in x16 A JPWR2 Slot3 PCI-E 2.0 x8 USB4/5 USB2/3 JPRST1 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 LED4 JPB1 LED6 LAN2 LAN1 Fan4 CPU Board Slot 2 JL1 JP21 T-SGPIO1 3-35 X8OBN-F Platform User's Manual Rear UID LED UID LED Status The rear UID LED is located at LED6 on the backplane. This LED is used in Color/State OS Status conjunction with the rear UID switch to provide easy identification of a system that might be in need of service. Refer to UID Switch on Page 3-15 for more information. Blue: On Windows OS Unit Identified Blue: Blinking Linux OS Unit Identified BMC Heartbeat LED BMC Heartbeat LED Status A BMC Heartbeat LED is located at LED4 on the baseboard. When LED4 is blinking, BMC functions normally. See the table at right for more information. Color/State Green: Blinking Definition BMC: Normal Note: LED Indicators that are not documented in the manual are for testing only. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard JF1 Fan6 IPMI LAN USB 0/1 COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 CPU Board Slot 2 Fan 10 Fan 9 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 JPWR3 A J32 J25 UID JPL1 A. Rear UID LED JP3 Fan7 Slot9 PCI-E 2.0 x8 Slot7 PCI-E 2.0 x8 J26 Slot6 PCI-E 2.0 x16 PLX PCI Bridge Battery JPWR2 BT1 JD1 JBT1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 I-SATA4 Buzzer I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 3-36 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 JL1 JP21 T-SGPIO1 PWR 2 Slot4 PCI-E 2.0 x16 JP22 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 T-SGPIO2 BMC CTRL I/O Hub 1 JPG1 B JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 B. BMC Heartbeat LED Chapter 3: Installation 3-12 Serial ATA Connections Serial_ATA Pin Definitions Serial ATA Ports There are six Serial ATA Ports (ISATA0 ~I-SATA5) located on the X8OBN-F. These ports, supported by the Intel ICH10R South Bridge, provide serial-link signal connections, which are faster than the connections of Parallel ATA. See the table on the right for pin definitions. Pin# Definition 1 Ground 2 TX_P 3 TX_N 4 Ground 5 RX_N 6 RX_P 7 Ground Note: For more information on SATA HostRAID configuration, please refer to the Intel SATA HostRAID User's Guide posted on our Website @ http:// www.supermicro.com.. JWD1 JOH1 KB/Mouse X8OBN-F Baseboard JF1 Fan6 IPMI LAN USB 0/1 COM1 FP CRTL Rev. 1.01 CPU Board Slot 4 Fan12 Fan5 J30 J29 Fan 11 VGA CPU Board Slot 3 JP18 JP19 JP17 JPT1 JUID_OW1 Fan3 CPU Board Slot 1 LAN CTRL JP16 JPWR4 Fan8 Slot10 PCI-E 2.0 x16 A. I-SATA0 JPWR3 Fan 10 Fan 9 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 JPL1 J32 J25 CPU Board Slot 2 UID B. I-SATA1 JP3 Fan7 Slot9 PCI-E 2.0 x8 I/O Hub 1 Slot7 PCI-E 2.0 x8 JPG1 J26 Slot6 PCI-E 2.0 x16 JPWR1 Fan2 Slot5 PCI-E 2.0 x8 Battery JD1 Slot3 PCI-E 2.0 x8 JPME2 ICH10R USB4/5 USB2/3 Slot1 PCI-E 2.0 x8 in x16 JIPMB1 USB10 USB8 JWF1 JTPM1 F I-SATA4 E Buzzer D B I-SATA5 I-SATA3 I-SATA1 I-SATA2 I-SATA0 C A 3-37 COM2 Fan1 JPME1 Slot2 PCI-E 2.0 x8 in x16 JL1 JP21 T-SGPIO1 D. I-SATA3 F. I-SATA5 JPWR2 BT1 JBT1 PWR 2 Slot4 PCI-E 2.0 x16 PLX PCI Bridge C. I-SATA2 E. I-SATA4 JP22 T-SGPIO2 BMC CTRL JPRST1 LED4 PWR 1 I/O Hub 2 Slot8 PCI-E 2.0 x16 JPB1 LED6 LAN2 LAN1 Fan4 X8OBN-F Platform User's Manual Notes 3-38 Chapter 4: Troubleshooting Chapter 4 Troubleshooting 4-1 Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. Note: Always disconnect the power cord before adding, changing or installing any hardware components. Before Power On 1. Make sure that there are no short circuits between the baseboard and chassis. 2. Disconnect all ribbon/wire cables from the baseboard, including those for the keyboard and mouse. 3. Remove all add-on cards. 4. Install CPU Card1 first (-making sure it is fully seated) and connect the front panel connectors to the baseboard. No Power 1. Make sure that no short circuits between the baseboard and the chassis. 2. Make sure that the ATX power connectors are properly connected 3. Check that the 115V/230V switch on the power supply is properly set, if available. 4. Turn the power switch on and off to test the system, if applicable. 5. The battery on your baseboard may be old. Check to verify that it still supplies ~3VDC. If it does not, replace it with a new one. 4-1 X8OBN-F Platform User's Manual No Video 1. If the power is on but you have no video, remove all the add-on cards and cables. 2. Use the speaker to determine if any beep codes exist. Refer to the Appendix for details on beep codes. System Boot Failure If the system does not display POST or does not respond after the power is turned on, check the following: 1. Check for any error beep from the baseboard speaker. •If there is no error beep, try to turn on the system without DIMM modules. If there is still no error beep, try to turn on the system again with only one processor in CPU Socket#1. If there is still no error beep, replace the baseboard. •If there are error beeps, clear the CMOS settings by unplugging the power cord and contracting both pads on the CMOS Clear Jumper (JBT1). (Refer to Section 3-10 in Chapter 3.) 2. Remove all components from the baseboard, especially the DIMM modules. Make sure that the system's power is on and memory error beeps are activated. 3. Turn on the system with only one DIMM module. If the system boots, check for bad DIMM modules or slots by following the Memory Errors Troubleshooting procedure in this Chapter. Losing the System’s Setup Configuration 1. Make sure that you are using a high quality power supply. A poor quality power supply may cause the system to lose the CMOS setup information. Refer to Chapter 3 for details on recommended power supplies. 2. The battery on your baseboard may be old. Check to verify that it still supplies ~3VDC. If it does not, replace it with a new one. 3. If the above steps do not fix the Setup Configuration problem, contact your vendor for repairs. 4-2 Chapter 4: Troubleshooting Memory Errors When a No_Memory_Beep_Code is issued by the system, check the following: 1. Make sure that the memory modules are compatible with the system and that the DIMM modules are properly and fully installed. (For memory compatibility, refer to the Memory Compatibility Chart posted on our Website at http://www. supermicro.com.) 2. Check if different speeds of DIMMs have been installed. It is strongly recommended that the same RAM speed of DIMMs are used in the system. 3. Make sure that you are using the correct type of DDR3 Registered ECC1066 MHz SDRAM (recommended by the manufacturer). 4. Check for bad DIMM modules or slots by swapping a single module among all memory slots and check the results. 5. Make sure that all memory modules are fully seated in their slots. Follow the instructions given in Chapter 3. 6. Please follow the instructions given in the DIMM Population Tables listed on Page 3-11 to install your memory modules. When the System Becomes Unstable A. When the system becomes unstable during or after OS installation, check the following: 1. CPU/BIOS support: Check if your CPU is supported and if you have the latest BIOS installed. 2. Memory support: Make sure that the memory modules are supported by testing the modules using memtest86 or a similar utility. Note: Refer to the product page on our Website at http:\\www.supermicro. com for memory compatibility list. 3. HDD support: Check if all hard disk drives (HDDs) work properly. Replace the bad HDDs with good ones. 4. System cooling: Check system cooling to make sure that all heatsink fans, and CPU/system fans, etc., work properly. Check Hardware Monitoring settings in the BIOS to make sure that the CPU and System temperatures are 4-3 X8OBN-F Platform User's Manual within normal range. Also check the front panel Overheat LED and make sure that the Overheat LED is not on. 5. Adequate power supply: Make sure that the power supply provides adequate power to the system. Make sure that all power connectors are connected. Please refer to our Website for more information on minimum power requirement. 6. Proper software support: Make sure that the correct drivers are used. B. When the system becomes unstable before or during OS installation, check the following: 1. Source of installation: Make sure that the devices used for installation are working properly, including boot devices such as CD/DVD disc, CD/DVDROM. 2. Cable connection: Check to make sure that all cables are connected and working properly. 3. Using minimum configuration for troubleshooting: Remove all unnecessary components (starting with add-on cards first), and use minimum configuration (with a CPU and a memory module installed) to identify the trouble areas. Refer to the steps listed in Section A above for proper troubleshooting procedures. 4. Identifying bad components by isolating them: If necessary, remove a component in question from the chassis, and test it in isolation to make sure that it works properly. Replace a bad component with a good one. 5. Check and change one component at a time instead of changing several items at the same time. This will help isolating and identifying the problem. 6. To find out if a component is good, swap it with a new one to see if the system will work properly. If so, then the old component is bad. You can also install the component in question in another system. If the new system works, the component is good and the old system has problems. 4-2 Technical Support Procedures Before contacting Technical Support, please take the following steps. Also, please note that as a baseboard manufacturer, Supermicro also sells motherboards through its channels, so it is best to first check with your distributor or reseller for trouble- 4-4 Chapter 4: Troubleshooting shooting services. They should know of any possible problem(s) with the specific system configuration that was sold to you. 1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Question' (FAQ) sections in this chapter or see the FAQs on our Website (http://www.supermicro.com/) before contacting Technical Support. 2. BIOS upgrades can be downloaded from our Website (http://www.supermicro. com). 3. If you still cannot resolve the problem, include the following information when contacting Supermicro for technical support: •Baseboard model and PCB revision number •BIOS release date/version (This can be seen on the initial display when your system first boots up.) •System configuration 4. An example of a Technical Support form is on our Website at (http://www. supermicro.com). •Distributors: For immediate assistance, please have your account number ready when placing a call to our technical support department. We can be reached by e-mail at [email protected]. 4-3 Frequently Asked Questions Question: What are the various types of memory that my baseboard can support? Answer: The X8OBN supports Registered ECC DDR3 1066 MHz SDRAM memory. It is strongly recommended that you do not mix memory modules of different speeds and sizes. Please follow all memory installation instructions given on Page 3-11 in Chapter 3. Question: How do I update my BIOS? It is recommended that you do not upgrade your BIOS if you are not experiencing any problems with your system. Updated BIOS files are located on our website at http://www.supermicro.com. Please check our BIOS warning message and the information on how to update your BIOS on our website. Select your baseboard model and download the BIOS file to your computer. Also, check the current BIOS revision and make sure that it is newer than your BIOS before downloading. You 4-5 X8OBN-F Platform User's Manual can choose from the zip file and the .exe file. If you choose the zip BIOS file, please unzip the BIOS file onto a bootable USB device. Run the batch file using the format AMI.bat filename.rom from your bootable USB device to flash the BIOS. Then, your system will automatically reboot. Warning: Do not shut down or reset the system while updating BIOS to prevent possible system boot failure!) Note: The SPI BIOS chip used on this baseboard cannot be removed. Send your baseboard back to our RMA Department at Supermicro for repair. For BIOS Recovery instructions, please refer to the AMI BIOS Recovery Instructions posted at http://www.supermicro.com. Question: What's on the CD that came with my baseboard? Answer: The supplied compact disc has quite a few drivers and programs that will greatly enhance your system performance. We recommend that you review the CD and install the applications you need. Applications on the CD include chipset drivers for the Windows OS, security and audio drivers. Question: How do I handle the used battery? Answer: Please handle used batteries carefully. Do not damage the battery in any way; a damaged battery may release hazardous materials into the environment. Do not discard a used battery in the garbage or a public landfill. Please comply with the regulations set up by your local hazardous waste management agency to dispose of your used battery properly. 4-4 Returning Merchandise for Service A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your vendor for a Returned Merchandise Authorization (RMA) number. When returning to the manufacturer, the RMA number should be prominently displayed on the outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and handling charges will be applied for all orders that must be mailed when service is complete. For faster service, You can also request a RMA authorization online (http://www.supermicro.com). This warranty only covers normal consumer use and does not cover damages incurred in shipping or from failure due to the alternation, misuse, abuse or improper maintenance of products. During the warranty period, contact your distributor first for any product problems. 4-6 Chapter 4: AMI BIOS Chapter 5 BIOS 5-1 Introduction This chapter describes the AMI BIOS Setup Utility for the X8OBN-F Baseboard. The AMI ROM BIOS is stored in a Flash EEPROM and can be easily updated. This chapter describes the basic navigation of the AMI BIOS Setup Utility screens. Starting BIOS Setup Utility To enter the AMI BIOS Setup Utility screens, press the <Delete> key while the system is booting up. Note: In most cases, the <Delete> key is used to invoke the AMI BIOS setup screen. There are a few cases when other keys are used, such as <F1>, <F2>, etc. Each main BIOS menu option is described in this manual. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. Grayed-out options cannot be configured. Options in blue can be configured by the user. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it. Note: the AMI BIOS has default text messages built in. Supermicro retains the option to include, omit, or change any of these text messages. The AMI BIOS Setup Utility uses a key-based navigation system called "hot keys". Most of the AMI BIOS setup utility "hot keys" can be used at any time during the setup navigation process. These keys include <F1>, <F10>, <Enter>, <ESC>, arrow keys, etc. Note: Options printed in Bold are default settings. How To Change the Configuration Data The configuration data that determines the system parameters may be changed by entering the AMI BIOS Setup Utility. This setup utility can be accessed by pressing <Del> at the appropriate time during system boot. Note: For UEFI BIOS Recovery, please refer to the UEFI BIOS Recovery Instructions posted on our website at http://www.supermicro.com/support/ manuals/. 5-1 X8OBN-F Platform User's Manual Starting the Setup Utility Normally, the only visible Power-On Self-Test (POST) routine is the memory test. As the memory is being tested, press the <Delete> key to enter the main menu of the AMI BIOS Setup Utility. From the main menu, you can access the other setup screens. An AMI BIOS identification string is displayed at the left bottom corner of the screen below the copyright message. Warning! Do not upgrade the BIOS unless your system has a BIOS-related issue. Flashing the wrong BIOS can cause irreparable damage to the system. In no event shall Supermicro be liable for direct, indirect, special, incidental, or consequential damages arising from a BIOS update. If you have to update the BIOS, do not shut down or reset the system while the BIOS is updating. This is to avoid possible boot failure. 5-2 Main Setup When you first enter the AMI BIOS Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab on the top of the screen. The Main BIOS Setup screen is shown below. BIOS Information: The following BIOS information will be displayed: •BIOS Vendor: This item displays the name of the BIOS vendor. •Core Version: This item displays the version of the BIOS Core currently used in the system. •Project Version: This item displays the version of the motherboard currently used in the system. 5-2 Chapter 4: AMI BIOS •Build Date: This item displays the date when this BIOS was completed. Memory Information: The following memory information will be displayed: •Total Memory: This item displays the size of memory available in the system. System Language The feature allows the user to select a language setting for the Setup utility. The default setting is English. System Time/System Date These features allow the user to change the system time and date. Highlight System Time or System Date using the arrow keys. Enter new values through the keyboard and press <Enter>. Press the <Tab> key to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format. Note: The time is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00. Access Level The feature displays the privilege level that has been pre-set for the user for accessing the setup utility or the system. 5-3 X8OBN-F Platform User's Manual 5-3 Advanced Setup Configuration Use the arrow keys to select the Advanced Setup menu and press <Enter> to access the submenu items. PCI Subsystem Settings PCI Bus Driver Version: This feature displays the version number of the PCI Bus Driver used in this system. PCI Bus Driver Version: This item displays the version of the PCI bus driver currently used in the system. PCI ROM Priority This feature allows the user to specify which PCI Option ROM to use when multiple Option ROMs are installed in the system. The options are Legacy ROM and EFI (Extensible Firmware Interface)_Compatible ROM. Above 4G Decoding Select Enabled to allow a 64_bit_capable device to be decoded in the address space above 4G if 64-bit_PCI_decoding is supported by the system. The options are Enabled and Disabled. PCI Common Settings PCI Latency Timer Select a value to be used by the PCI Latency Timer Register in bus clock calculation. The options are 32 PCI Bus Clocks, 64 PCI Bus Clocks, 96 PCI Bus Clocks, 128 PCI Bus Clocks, 160 PCI Bus Clocks, 192 PCI Bus Clocks, 224 PCI Bus Clocks, and 248 PCI Bus Clocks. 5-4 Chapter 4: AMI BIOS VGA Palette Snoop If this feature is set to Enabled, a PCI card that does not have its own VGA color palette built-in will detect a video_card palette to mimic it for color scheme support. The options are Enabled and Disabled. PERR# Generation Select Enabled to allow a PCI device to generate a PERR number for a PCI Bus Signal Error Event. The options are Enabled and Disabled. SERR# Generation Select Enabled to allow a PCI device to generate an SERR number for a PCI Bus Signal Error Event. The options are Enabled and Disabled. PCI Express Device Settings Relaxed Ordering Select Enabled to allow a PCI-E transaction to be completed prior to other transactions that were already enqueued. This violates PCI strict-ordering rules. The options are Enabled and Disabled. Extended Tag Select Enabled to allow a PCI-E device to use the 8-bit Tag field as a requester. The options are Enabled and Disabled. No Snoop Select Enabled to enable the "no_snoop bit" for a PCI-E device, which will reduce front_side bus traffic for performance enhancement. The options are Enabled and Disabled. Maximum Payload Select Auto to allow the system BIOS to automatically set the maximum payload value for a PCI-E device to enhance system performance. The options are Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes. Maximum Read Request Select Auto to allow the system BIOS to automatically set the maximum Read Request size for a PCI-E device to enhance system performance. The options are Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes. 5-5 X8OBN-F Platform User's Manual PCI Express Link Settings ASPM Support This feature allows the user to set the Active State Power Management (ASPM) level for a PCI-E device. Select Force L0 to force all PCI-E links to operate at L0 state. Select Auto to allow the system BIOS to automatically set the ASPM level for the system. Select Disabled to disable ASPM support. The options are Disabled, Force L0, and Auto. Warning: Enabling ASPM support may cause some PCI-E devices to fail! Extended Synch Select Enabled to generate extended synchronization patters to enhance system performance. The options are Disabled and Enabled. ACPI (Advanced Configuration and Power Interface) Settings This feature allows the user to set Advanced Configuration and Power Interface parameters for this system. Enable ACPI Auto Configuration Select Enabled to allow the system BIOS to automatically configure ACPI parameters for the system. The options are Disabled and Enabled. Enable Hibernation Select Enabled for Hibernation support which will allow a system to enter an OS/S4 state. Hibernation may not be supported by some operation systems. The options are Enabled and Disabled. ACPI Sleep State Use this feature to set the highest ACPI sleep state when the suspend button is pressed. The options are S1 (CPU_Stop_Clock) and Suspend Disabled. Trusted Computing This feature allows the user to configure Trusting Computing settings. TPM Configuration This future allows the user to set Trusted Platform Module Configuration settings. 5-6 Chapter 4: AMI BIOS TPM Support Select Enabled to enable TPM (Trusted Platform Module) support for system security and data integrity. The options are Disabled and Enabled. If this option is set to Enabled, the following items will display. TPM State Select Enabled to display the status of TPM support for this system. The options are Disabled and Enabled. Please note that a system reboot is needed before a change on the TPM state to take effect. Pending TPM Operation This feature is used to schedule a TPM operation that is pending. Select "Enable Take Ownership" to allow the pending TPM operation to take precedence over other operations in the queue and be processed and executed immediately. If the option "Disable Take Ownership" is selected, the pending TPM operation will not take precedence over other operations and will be processed based on the order that are placed in the queue. Select the option "TPM Clear" to delete all pending TPM operations from the queue. If the option "None" is displayed, there is no pending TPM operation in the queue. Please note that a system reboot is needed for any change on the feature to become effective. The options are None, Enable Take Ownership, Disable Take Ownership, and TPM Clear. Current TPM Status Information This feature displays the current status of the TPM items listed below. TPM Enabled State Select Enabled to display the status of "TPM Enabled" in this system. The options are Disabled and Enabled. TPM Active State Select Deactivate to disable TPM support for this system. The options are Deactivated and Activate. TPM Owner Status This feature lists the status of the TPM Owner. The default setting is UnOwned which indicates that there is no owner listed for TPM support. WHEA Configuration This feature allows the user to configure WHEA (Windows Hardware Error Architecture) settings. 5-7 X8OBN-F Platform User's Manual WHEA Support Select Enabled to enable WHEA support which will provide a common infrastructure for the system to handle hardware errors on the Windows OS platforms in order to reduce system crashes due to hardware errors and to enhance system recovery and health monitoring. The default setting is Enabled. CPU Configuration CPU Configuration This feature allows the user to configure CPU support settings. It also displays the status of the processor used in the system. •CPU Type: This item displays the CPU type for the motherboard. •Physical Processors: This item displays the number of physical processors used in this system. •Logical Processors: This item displays the number of logical processors available for this system. Socket 0 ~ Socket 7 CPU Information •CPU Type •CPU Signature •Microcode Patch •Max Processor Speed/Min Processor Speed: This item displays the maximum and minimum speed of the processor used in the system. •Processor Cores: This item indicates the number of processor cores available in the system. •Intel HT Technology: This item indicates if Intel Hyper-Threading Technol- ogy is supported by the system. Intel TH Technology is used to enhance CPU performance. •Intel VT-x Technology: This item indicates if Intel Virtualization Technology is supported by the motherboard. •L1 Data Cache/L1 Code Cache/L2 Cache/L3 Cache •CPU Speed: This item displays the CPU speed of the motherboard. 5-8 Chapter 4: AMI BIOS •64-bit: This item indicates if 64-bit is supported by the CPU. CPU Spread Spectrum Select Enable to enable CPU Clock Spectrum support, which will allow the BIOS to monitor and attempt to reduce the level of Electromagnetic Interference caused by the components whenever needed. The options are Disabled and Enabled. Hyper-threading Select Enabled to use Hyper-Threading Technology, which will result in increased CPU performance. The options are Disabled and Enabled. Active Processor Core Select Enabled to use a processor's second core and beyond. (Please refer to Intel's website for more information.) The options are All, 1 and 2. Limit CPUID Maximum This feature allows the user to set the maximum CPU ID value. Enable this function to launch the legacy operating systems that cannot support processors with extended CPUID functions. The options are Enabled and Disabled (for the Windows OS.) Execute Disable Bit Capability (Available when supported by the OS and the CPU) Set to Enabled to support Execute Disable Bit which will allow the processor to designate areas in the system memory where an application code can execute and where it cannot, thus preventing a worm or a virus from flooding illegal codes to overwhelm the processor or damage the system during an attack. The default is Enabled. (Refer to Intel and Microsoft web Sites for more information.) Hardware Prefetcher (Available when supported by the CPU) If enabled, the hardware prefetcher will prefetch streams of data and instructions from the main memory to the L2 cache in the forward or backward manner to improve CPU performance. The options are Disabled and Enabled. Adjacent Cache Line Prefetch (Available when supported by the CPU) If this item is set to Disabled, the CPU prefetches the cache line for 64 bytes. The CPU prefetches both cache lines for 128 bytes as comprised if this item is set to Enabled. The options are Disabled and Enabled. Intel® Virtualization Technology (Available when supported by the CPU) Select Enabled to use Intel Virtualization Technology which will allow one platform to run multiple operating systems and applications in independent partitions, creat- 5-9 X8OBN-F Platform User's Manual ing multiple "virtual" systems in one physical computer. The options are Enabled and Disabled. Note: Please reboot the system for any change in this setting to take effect. Please refer to Intel’s website for detailed information. Power Technology Use this feature to select power management features for the system. Select Energy Efficient to minimize power use. Select Custom to customize power use settings. The options are Disabled, Energy Efficient and Custom. EIST (Available when supported by the OS and the CPU) EIST (Enhanced Intel SpeedStep Technology) allows the system to automatically adjust processor voltage and core frequency in an effort to reduce power consumption and heat dissipation. Please refer to Intel’s web site for detailed information. The options are Disabled and Enabled. Turbo Boost Mode (Available when EIST Tech. is enabled) Select Enabled to enable Turbo Mode support to boost system performance. The options are Enabled and Disabled. Performance/Watt (Available when supported by the OS and the CPU Select Optimized to activate the Turbo Boost mode after the highest performance power state has lasted more than two seconds. Select Traditional to use the Turbo mode whenever possible. The options are Traditional and Optimized. P-STATE Coordination (Available when supported by the OS and the CPU This feature allows the user to decide how to change a P-State Coordination type. A P-state is the operational state when a processor/core is performing meaningful and useful tasks. The options are HW_All (All Hardware-related events), SW_All (All Software-related events), and SW_Any (Any Software-related events). CPU C3 Report (Available when the C-State Tech is enabled) This feature allows the user to decide at what power state should the CPU treat it as a CPU C3 state and report it to the OS as so. Select ACPI C-2 to report an ACPI C-2 event as a CPU C3 state to the OS. Select ACPI C-3 to report an ACPI C-3 event as a CPU C3 state to the OS. The options are ACPI-C2, ACPI-C-3, and Disabled. CPU C6 Report (Available when the C-State Tech is enabled) Select Enabled to report a CPU C6 (ACPI C-3) event to the OS. The options are Enabled and Disabled. 5-10 Chapter 4: AMI BIOS Package C-State Limit (Available when the C-State Tech is enabled) If this package is set to Auto, the AMI BIOS will automatically set a limit on the register of the C-State package. The options are No Limit, C0, C1, C3, C6, and C7. Local APIC (Available when supported by the CPU and the OS) The local Advanced Programmable Interrupt controller (Local APIC), embedded in a CPU, manages all external interrupts for the CPU in a 4-way or 8-way system. It also interacts with the interrupts that are generated by other Local APIC controllers inside other CPUs. If this feature is set to Auto, the AMIBIOS will automatically detect if the system is using the Nehalem processor or the Westmere EX processor. If the system uses the Nehalem EX processor, the BIOS will select xAPIC to boost system performance. If the system uses the Westmere EX processor, the BIOS will select x2APIC to boost performance. If your system uses the Westmere processor and your OS does not support x2APIC, please select Compatible to enhance your system performance. The options are Compatible and Auto. Note: Currently, x2APIC is supported by newer operating systems such as Windows 2008 R2 SP1 OS or Redhat 6.0 (or newer) OS. Runtime Error Logging Runtime Error Logging Select Enabled to support Runtime Error Logging. The options are Enabled and Disabled. If this feature is set to Enabled, the following items will display: PCI Error Logging Support Select Enabled to enable error logging occurred in PCI/PCI-E connections. The options are Enabled and Disabled. 5-11 X8OBN-F Platform User's Manual Memory Correctable Error Threshold This feature allows the user to enter the threshold value for memory correctable errors. The default setting is 10. Legacy OpROM (Option ROM) Configuration Legacy OpROM Support Use this feature to configure Option ROM settings which will allow the system to boot up via a legacy network device. Onboard Gigabit LAN 0/ Onboard Gigabit LAN 1 Select Enabled to boot up the system via a legacy network device installed on Onboard G-LAN Port 0 or G-LAN Port 1. The options are Enabled and Disabled. Select Option ROM [PXE} Slot1 Option ROM~Slot10 Option ROM Select Enabled to boot up the system via a legacy mass storage device installed a slot specified. The options are Enabled and Disabled. SATA Configuration When this submenu is selected, the AMI BIOS automatically detects the presence of the SATA devices and displays the following items: •SATA Port0/SATA Port1/SATA Port2/SATA Port3/SATA Port4/SATA Port5 SATA Mode Use this feature to set the SATA mode for a SATA port selected by the user. Select IDE mode to configure the SATA drive as an IDE drive. Select AHCI Mode to enable the SATA drive to support AHCI Interface (Advanced Host Controller Interface). Select RAID Mode to enable the SATA drive for RAID support. The options are IDE Mode, AHCI Mode and RAID Mode. When AHCI is selected, the item-AHCI CodeBase will display: AHCI CodeBase (Available when RAID or AHCI is selected) Select BIOS Native Module to use the BIOS Native Mode for the AHCI Interface. Select Intel AHCI ROM to use the Intel AHCI ROM for the AHCI Interface. (Take caution when using this function for this mode is for advanced programmers only.) When RAID is selected, the items: "AHCI CodeBase" (above), and "ICH RAID Code Base" will appear. 5-12 Chapter 4: AMI BIOS ICH RAID Code Base (Available when the option-RAID is selected) Select Intel to use Intel SATA RAID firmware for Intel SATA RAID configuration. Select Adaptec to use Adaptec firmware for Adaptec SATA RAID configuration. The options are Intel and Adaptec. SATA Port0 Configuration/SATA Port1 Configuration/SATA Port2 Configuration/SATA Port3 Configuration//SATA Port4 Configuration//SATA Port51 Configuration These submenus allow the user to configure the following item for a SATA port selected by the user. eSATA Port Support Select Enabled to enable a SATA port specified by the user for external SATA connection support. The options are Enable and Disabled. USB Configuration •USB Devices: This feature displays the status of the USB devices detected in the system. Legacy USB Support Select Enabled to support Legacy USB devices. If this item is set to Auto, the AMI BIOS will automatically enable Legacy USB support if a legacy USB device is detected. The settings are Enabled, Disabled and Auto. EHCI Hand-Off Select Enabled to support the BIOS-Enhanced Host Controller Interface to provide a workaround solution for an operating system that does not have EHCI Hand-Off support. When enabled, the EHCI Interface will be changed from the BIOS-controlled to the OS-controlled. The options are Disabled and Enabled. USB Hardware Delay USB Transfer Timeout This setting allows you to decide how long the system should wait in an attempt to detect the presence of a USB Mass Storage Device before a USB Transfer is executed. The options are 10 Seconds, 20 Seconds, 30 Seconds and 40 Seconds. Device Reset Timeout This setting allows you to decide how long the system should wait in an attempt to detect the presence of a USB Mass Storage Device before it proceeds with the next operation during POST. The options are 10 Seconds, 20 Seconds, 30 Seconds and 40 Seconds. 5-13 X8OBN-F Platform User's Manual Device Power-up Delay Select Auto to use the default maximum time value for a USB device to wait before it reports itself to the Host Controller. The default maximum wait time for a root port is 100 ms. The maximum wait time for a Hub port is determined by the Hub Descriptor. Select Manual to manually enter a maximum wait time for a USB device before this device reports itself to the Host Controller. The options are Auto and Manual. Hardware Monitoring Configuration This feature allows the user to monitor system health and review the status of each item as displayed. CPU Overheat Alarm This option allows the user to select the CPU Overheat Alarm setting that determines when the CPU OH alarm will be activated to provide warning of possible CPU overheat. The options are: •The Early Alarm: Select this setting to trigger the CPU overheat alarm as soon as the CPU temperature reaches the CPU overheat threshold as predefined by the CPU manufacturer. •The Default Alarm: Select this setting to trigger the CPU overheat alarm when the CPU temperature reaches about 5oC above the threshold temperature as predefined by the CPU manufacturer to give the CPU and system fans additional time needed for CPU and system cooling. Warning! To avoid possible system overheating, please be sure to provide adequate airflow to your system. Fan Speed Control Modes This feature allows the user to decide how the system controls the speeds of the onboard fans. The CPU temperature and the fan speed are correlated. When the CPU on-die temperature increases, the fan speed will also increase for effective system cooling. Select "Full Speed/FS" to allow the onboard fans to run at full speed for maximum cooling. The FS setting is recommended for special system configuration or debugging. Select "Performance/PF" for better system cooling. The PF setting is recommended for high-power-consuming and high-density systems. Select "Balanced/BL" for the onboard fans to run at a speed that will balance the needs between system cooling and power saving. The BL setting is recommended for regular systems with normal hardware configuration. Select "Energy Saving/ES" for best power efficiency and maximum quietness. The Options are: Full Speed/FS, Performance/PF, Balanced/BL, and Energy Saving/ES. 5-14 Chapter 4: AMI BIOS Fan Speed Readings The following fan speeds are displayed: Fan1 Speed~Fan 12 Speeds Baseboard Voltage and Temperature The he following temperature and voltage settings will be displayed (in degrees in Celsius and Fahrenheit) as detected by the BIOS: •System Temperature, +1.8V Aux, +1.2V BMC, +1.0V NIC, +1,1V AUX, +1.0V PEX, +5.0V, +1.1V, +1.8V, +12.0V, +1.5V, VBAT, +3.3V, and +3.3V VSB. CPU0 Voltage and Temperature~CPU7 Voltage and Temperature The following temperature and voltage settings of a CPU specified will be displayed as detected by the BIOS: •CPU Temperature Low – This level is considered as the ‘normal’ operating state. The CPU temperature is well below the CPU ‘Temperature Tolerance’ level. The onboard fans and CPU run normally as configured in the BIOS. User intervention: No action required. Medium – The processor is running warmer. This is a ‘precautionary’ level and generally means that there may be factors contributing to this condition, but the CPU is still within its normal operating state and the CPU ‘Temperature Tolerance’ level. The onboard fans and CPU run normally as configured in the BIOS. The fans may adjust to a faster speed depending on the Fan Speed Control settings. User intervention: No action is required. However, consider checking the CPU fans and the chassis ventilation for blockage. High – The processor is running hot. This is a ‘caution’ level since the CPU’s ‘Temperature Tolerance’ has been reached or exceeded. The overheat alarm may be triggered. The system may shut down if it continues for a long period to prevent damage to the CPU. •CPU Vcore, CPU Vcache, CPU Millbrook 1.1V, CPU Branch0 VDD 1.5V, and CCPU Branch1 VDD 1.5V Super IO Configuration (for the W83527 HG chip) •Super IO Chip: This item displays the status of the onboard Super IO chip. 5-15 X8OBN-F Platform User's Manual Watchdog Function If enabled, the WatchDog Timer will cause the system to reboot when the system is inactive for more than 5 minutes. The options are Enabled and Disabled. Super IO Configuration (for the WPCM450 chip) Super IO Configuration (Winbond WPCM450) •Super IO Chip: This item displays the status of the onboard Super IO chip. Watchdog Function Select Enabled to enable the Watch Dog Timer. The options are Enabled and Disabled. Serial Port 0 Configuration/Serial Port 1 Configuration Serial Port Select Enabled to enable a serial port specified by the user. The options are Enabled and Disabled. Device Settings This feature indicated if reset is required or not for a serial port specified. Change Settings Use this feature to set the optimal Environment_Control_Interface (PECI) setting for a serial port specified. The default setting is Auto, which will allow the AMI BIOS to automatically select the best setting for the PECI platform. Device Mode Use this feature to select the desired mode for a serial port specified. The options are Normal and High Speed. Serial Port Console Redirection •COM 1/COM2 These two submenus allow the user to configure the following Console Redirection settings for a COM Port specified by the user. Console Redirection Select Enabled to use a COM Port selected by the user for Console Redirection. The options are Enabled and Disabled. 5-16 Chapter 4: AMI BIOS Console Redirection Settings This feature allows the user to specify how the host computer will exchange data with the client computer, which is the remote computer used by the user. Terminal Type This feature allows the user to select the target terminal emulation type for Console Redirection. Select VT100 to use the ASCII Character set. Select VT100+ to add color and function key support. Select ANSI to use the Extended ASCII Character Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8. Bits Per second Use this feature to set the transmission speed for a serial port used in Console Redirection. Make sure that the same speed is used in the host computer and the client computer. A lower transmission speed may be required for long and busy lines. The options are 9600, 19200, 57600 and 115200 (bits per second). Data Bits Use this feature to set the data transmission size for Console Redirection. The options are 7 Bits and 8 Bits. Parity A parity bit can be sent along with regular data bits to detect data transmission errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits is even. Select Odd if the parity bit is set to 0, and the number of 1's in data bits is odd. Select None if you do not want to send a parity bit with your data bits in transmission. Select Mark to add a mark as a parity bit to be sent along with the data bits. Select Space to add a Space as a parity bit to be sent with your data bits. The options are None, Even, Odd, Mark and Space. Stop Bits A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard serial data communication. Select 2 Stop Bits if slower devices are used. The options are 1 and 2. Flow Control This feature allows the user to set the flow control for Console Redirection to prevent data loss caused by buffer overflow. Send a "Stop" signal to stop sending data when the receiving buffer is full. Send a "Start" signal to start sending data when the receiving buffer is empty. The options are None, Hardware RTS/ CTS, and Software Xon/Xoff. 5-17 X8OBN-F Platform User's Manual Resolution 100x31 Select Enabled for extended-terminal resolution support. The options are Disabled and Enabled. Legacy OS Redirection Use this feature to select the number of rows and columns used in Console Redirection for legacy OS support. The options are 80x24 and 80x25. Serial Port for Out-of-Band Management/Windows Emergency Management Services (EMS) The submenu allows the user to configure the following Console Redirection settings to support Out-of-Band Serial Port management. Console Redirection Select Enabled to use COM Port1 for Console Redirection. The options are Enabled and Disabled. Out-of_Band Management Port This feature allows the user to select a serial port to be used by the Windows Emergency Management Services (EMS) for remote system management during an emergency. The options are COM 1 and COM 2. Data Bits This feature allows the user to select data bits for console redirection transmission. The options are 7 Bits and 8 Bits. Parity A parity bit can be sent with the data bits for data transmission errors. Select Even if the parity bit is set to 0 and the number of 1's in data bits is even. Select Odd if the parity bit is set to 0 and the number of 1's in data bits is odd. Select None if you do not want to send a parity bit with your data bits in transmission. Select Mark to add a mark as a parity bit to be sent with the data bits. Select Space to add a Space as a parity bit to be sent with your data bits. The options are None, Even, Odd, Mark and Space. Stop Bits A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard serial data communication. Select 2 Stop Bits if slower devices are used. Terminal Type This feature allows the user to select the target terminal emulation type for Console Redirection. Select VT100 to use ASCII Character set, Select VT100+ to also include color, function key support. Select ANSI to use Extended ASCII Char- 5-18 Chapter 4: AMI BIOS acter Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8. Network Stack Network Stack Select Enabled enable PXE (Preboot Execution Environment) or UEFI (Unified Extensible Firmware Interface) for network stack support. The options are Enabled and Disabled. 5-4 Chipset Use the arrow keys to select Chipset and press <Enter> to access the submenu items. This submenu allows the user to configure chipset settings. North Bridge This submenu allows the user to configure the following North Bridge parameters. Boxboro IOH Configuration •NB Revision: This item displays the Boxboro IOH revision number. Intel® VT for Direct I/O Configuration This feature allows the user to configure Intel Virtualization Technology for Directed I/O settings. 5-19 X8OBN-F Platform User's Manual Intel® VT-d Select Enabled to enable Intel Virtualization Technology support for Direct I/O VT-d by reporting the I/O device assignments to VMM through the DMAR ACPI Tables. This feature offers fully-protected I/O resource-sharing across the Intel platforms, providing the user with greater reliability, security and availability in networking and data-sharing. The options are Enabled and Disabled. Interrupt Remapping Select Enabled to support VT-d Engine Interrupt Remapping. The options are Enabled and Disabled. Coherency Support Select Enabled to enable Non-Isoch VT-d Engine Coherency support. The options are Enabled and Disabled. ATS Support Select Enabled to enable VT-d Engine Address Translation Services support. The options are Enabled and Disabled. Pass-through DMA Select Enabled to enable Isoch/Non-Isoch VT-d Engine Pass-through DMA support. The options are Enabled and Disabled. Intel® I/OAT The Intel I/OAT (I/O Acceleration Technology) significantly reduces CPU overhead by leveraging CPU architectural improvements, freeing resources for more other tasks. The options are Disabled and Enabled. DCA Support (Available when Intel I/OAT is enabled) Select Enabled to use Intel's DCA (Direct Cache Access) Technology for data transferring enhancement. The options are Enabled and Disabled. PCIe Gen1 Device Support (Available when Intel I/OAT is enabled) Select Enabled to support PCI-Express Gen. 1 devices. The options are Enabled and Disabled. IOH PCIe Port Bifurcation Support This feature displays the following IOH PCIe Port Bifurcation Control settings, which indicate how PCI-Express connections are split into different PCI-E signals for various device support. •IOH1/IOU2 5-20 Chapter 4: AMI BIOS •IOH1/IOU0 •IOH1/IOU1 •IOH2/IOU2 •IOH2/IOU0 •IOH2/IOU1 IOH Thermal Sensors This feature allows the user to configure integrated thermal sensor settings embedded in the 7500 chipset. Thermal Sensors Select Enabled to enable integrated thermal sensors embedded in the 7500 chipset. The options are Enabled and Disabled. •Low Threshold: This item displays the value of the low thermal threshold. •High Threshold: This item displays the value of the high thermal threshold. •Catastrophe Threshold: This item displays the value of the catastrophic threshold, beyond which the system enters into the catastrophic state. QPI Link QuickPath Interconnect (QPI) is the connection between the processors and the I/O hubs (IOH's). This submenu allows the user to configure the following QPI settings. •Current QPI Link Speed: This item displays the current QPI Link speed. •Current QPI Link Frequency: This item displays the current QPI Link fre- quency. CSI (Common System Interface) Link Speed This feature allows the user to select the speed for CSI (Common System Interface) Link, which is the former name for QPI Link. Select Fast for POR (Power_On Reset)-related devices. The options are Slow and Fast. 5-21 X8OBN-F Platform User's Manual QPI Link Frequency Select This feature allows the user to set the QPI Link Frequency. Select Auto for the AMI BIOS to automatically set the QPI Link Frequency for optimal system performance. The options are Auto, 4.8 GT/s, 5.866 GT/s, and 6.4 GT/s. CRC Mode Use this feature to enable the CRC (Cyclic Redundancy Check) mode in CSI and select the method used by the CRC mode to detect any accidental changes to raw computer data occurred in digital networks or storage devices. The options are 8_bit CRC and 16_bit Rolling CRC. CSI (Common System Interface) Scrambling Select Enabled to support CSI data scrambling via 0:10h/11h:0:44h:22. The options are Enabled and Disabled. Logical Interrupt Mode Use this feature to select the Logical Interrupt mode for the programmable interrupt controller (PIC) embedded in a multiple-processor system. Select Flat mode for the PIC to process interrupts in the linear, sequential format. Select Cluster Mode for the PIC to process interrupts in the cascade format. The options are Flat Mode and Cluster Mode. Cluster Mode Check Sampling Select Enabled for a system to check the APIC ID for non-zero. APIC ID is used to identify a processor in multi-processor systems. The options are Enabled and Disabled. MMIOH Size per IOH Use this feature to select the MMIOH Size to be allocated to every IOH in the system. The options are 2G, 4G, 6G and 8G. Intel reference Code This item displays Intel IOH Reference code for the system. Memory Information The item displays the following memory information: •Total Memory: This item displays the total memory available in the system. •Current Memory Mode: This item displays the current memory mode used in the system. 5-22 Chapter 4: AMI BIOS •Current Memory Speed: This item displays the current memory speed of the system. •Mirroring: This item indicates if memory mirroring is supported by the system for data security enhancement. •Sparing: This item indicates if memory sparing is supported by the system for memory performance enhancement. Memory Configuration This feature allows the user to configure the following memory settings: Memory Init mode Select Serial to set the memory initialization mode to Serial. Select Parallel to set the memory initialization mode to Parallel. The options are Serial and Parallel. Page Policy This feature allows the user to select the memory page policy for virtual memory support. Select Open for a memory control unit to issue a command to open a memory page. Select Closed for the memory control unit to issue a command to close a memory page. Select Adaptive to provide a flexible page policy to better support each individual event. Select Multi-Cas Widget to simultaneously provide memory support to multiple users in a multi-casting format. The options are Closed, Open, Adaptive and Muliti-Cas Widget. Mapping Policy This feature allows the user to set the policy for memory mapping, which is a file used by the virtual memory system of the OS to access the data in the file system directly instead of accessing the contents stored in a file, one piece at a time, to improve I/O performance. The options are Closed and Open. Scheduler Policy This feature allows the user to set the policy for memory scheduling for dynamic RAM accessing. The options are Adaptive, Static Trade Off, Static Read Primary and Static Write Primary. NUMA Select Enabled to enable Non-Uniform Memory Access support to improve CPU performance. The options are Enabled and Disabled. DDR Speed This feature allows the user to set a speed for onboard DDR modules. Select Auto for the AMI BIOS to set the DDR speed based on the DDR specifications 5-23 X8OBN-F Platform User's Manual detected in the system. The options are Auto, Force DDR3 800, Force DDR3 978 and Force DDR3 1067. High Temperature Select Enabled for high temperature support for onboard memory modules. The options are Enabled and Disabled. Hemisphere Select Enabled for Hemisphere Mode support to improve the latency of individual memory accessing. The options are Enabled and Disabled. Patrol Scrub It is a memory error-correction scheme that works in the background looking for and correcting resident errors. The options are Enabled and Disabled. Patrol Scrub Interval Use this feature to set the hours needed for each Patrol Scrub cycle to complete the task. Select 5 hours for the AMI BIOS to automatically set the time needed for a Patrol Scrub cycle to complete the task. The default setting is 5 (hours). Socket 0 Branch 0 Sparing/Socket 0 Branch 1 Sparing/ Socket 1 Branch 0 Sparing/Socket 1 Branch 1 Sparing/~/Socket 7 Branch 1 Sparing Use this feature to enable or disable memory sparing support for the memory modules specified. The options are Disabled, DIMM Sparing Enable, and Rank DIMM Enable. Spare Copy Duration Use this feature to set the hours needed for each Spare-Copy cycle to complete the task. Select 5 hours for the AMI BIOS to automatically set the time needed for spare copy to complete the task. The default setting is 5 (hours). Mirroring/Migration Select Mirror to support memory mirroring to enhance data security. Select Migration to support memory Migration. The options are Disabled, Mirror, and Migration. Mirroring/Migration Error This item indicates the Mirror/Migration Error threshold. Memory Throttling Select Enabled for closed loop memory thermal throttling support. The options are Enabled and Disabled. 5-24 Chapter 4: AMI BIOS South Bridge This submenu allows the user to configure the following South Bridge settings. South Bridge Chipset Configuration This feature allows the user to configure the following South Bridge parameters. SMBus Controller Select Enabled to enable the SMBus (System Management Bus) controller to improve system management. The options are Enabled and Disabled. GbE Controller Select Enabled to enable the Gigabit PCI-Express controller to enhance PCI-E performance. The options are Enabled and Disabled. Wake On LAN from S5 Select Enabled to "wake up" the system when a network device installed in a LAN port receives a signal while the system is in the S5 state. The options are Enabled and Disabled. Restore on AC Power Loss Use this feature to set the power state after a power outage. Select Power-Off for the system power to remain off after a power outage. Select Power-On for the system power to be turned on after an outage. Select Last State to allow the system to resume its last state before a power loss. The options are Power-On, Power-Off and Last State. Power Button Function If this item is set to Instant_Off, the system will power off immediately as soon as the user presses the power button. If set to 4_Second_Override, the system will power off when the user presses the power button for 4 seconds or longer. The options are Instant_Off and 4_Second_Override. High precision Event Timer Configuration This feature allows the user to configure the following South Bridge parameters. High Precision Event Timer Select Enabled to activate the High Precision Event Timer (HPET) that produces periodic interrupts at a much higher frequency than a Real-time Clock (RTC) does in synchronizing multimedia streams, providing smooth playback and reducing the dependency on other timestamp calculation devices, such as an x86 RDTSC In- 5-25 X8OBN-F Platform User's Manual struction embedded in the CPU. The High Precision Event Timer is used to replace the 8254 Programmable Interval Timer. The options are Enabled and Disabled. PCI-Express_Port Configuration This feature allows the user to configure the following PCI-E_port settings: PCI-Express Port 1~ PCI-Express Port 5 Select Enabled to enable the PCI-E port specified by the user. The options are Enabled and Disabled. USB Configuration This submenu allows the user to configure the following USB settings. All USB Devices Select Enabled to enable all USB devices in the system. The options are Enabled and Disabled. USB 2.0 (EHCI) Support Select Enabled for USB 2.0 EHCI (Extended Host Controller Interface) support. The options are Enabled and Disabled. EHCI Controller 1/2 Select Enabled to enable the EHCI controller specified by the user to enhance USB communication. The options are Enabled and Disabled. UHCI Controller1~UHCI Controller 6 Select Enabled to enable the UHCI (Universal Host Controller Interface) controller specified by the user to enhance USB1.0 communication. The options are Enabled and Disabled. USB Port0~USB Port11 Select Enabled to enable the USB port specified by the user for USB communication. The options are Enabled and Disabled. 5-26 Chapter 4: AMI BIOS 5-5 Server Management This section allows the user to configure Server Management settings. BMC Support Select Enabled to enable the Baseboard Management Controller. The options are Enabled and Disabled. System Event Log Enabling/Disabling Options Use this feature to enable or disable the following System Event Log (SEL) settings. SEL Components Select Enabled to support all features of System Event Logging (SEL) during bootup. The options are Enabled and Disabled. Erasing Settings This feature allows the user to decide when to erase a System Event Log. Erase SEL Select Yes to erase all System Event Logs. The options are Yes and No. 5-27 X8OBN-F Platform User's Manual When SEL is Full This feature allows the user to decide what the system shall do when the System Event Log is full. This feature is not available when the FRB-2 Timer is disabled. The options are Do Nothing, Power Down and Reset. Custom EFI Logging Options Use this feature to customize the settings of Extensible_Firmware_Interface (EFI) Logging between an operation system and the system platform firmware. Log EFI Status Codes Select Both to record the microcodes for both OS and the system platform firmware during EFI logging. The default setting is Both. Note: Be sure to reboot the computer for all the changes on the setting indicated above to take effect. BMC Network Configuration Use this feature to configure BMC (Baseboard Management Controller) Network settings. LAN Channel 1/ LAN Channel 2 Update IPMI LAN Configuration Select Yes to update the following IPMI settings at the next boot. •Configuration Address Use this feature to select the source or the parameter of an IP address for the LAN channel specified by the user. If Static is selected, you will need to know and manually enter the IP address for the LAN channel specified. If DHCP is selected, BIOS will search for a DHCP (Dynamic Host Configuration Protocol) server in the network it is attached to, and request the next available IP address. If "Do Nothing" is selected, BMC Network parameters will not be modified when the BIOS Setup Utility is in operation. The options are DHCP, Static, and Do nothing. •Current IP Address •Current Subnet Mask •Current MAC Address •Current Router IP Address •Current Router MAC Address 5-28 Chapter 4: AMI BIOS 5-6 iSCSI This section allows the user to configure iSCSI settings. iSCSI Initiator Name Use this feature to specify the name of your iSCSI initiator. This name will be unique worldwide. Be sure to use the iSCSI Qualified Name (iqn) format when naming your iSCSI Initiator. 5-7 Boot Configuration This section allows the user to configure Boot settings. 5-29 X8OBN-F Platform User's Manual Quiet Boot This feature allows the user to select the bootup screen display between the POST messages and the OEM logo. Select Disabled to display the POST messages. Select Enabled to display the OEM logo instead of the normal POST messages. The options are Enabled and Disabled. Fast Boot Select Enabled to skip certain tests during POST to reduce the time needed for system boot. This feature has no effect on BBS (BIOS Boot Specification) boot options. The options are Enabled and Disabled. Boot Graphics Adapter Priority This option allows the user to specify which graphics controller to be used as the primary boot device. The options are Auto and Onboard VGA Device. Setup Prompt Timeout This feature allows the user to specify how many seconds the system shall wait for the BIOS setup activation key to complete its tasks before the system resumes the normal operation. The default setting is 1 Second. Bootup Num-Lock Select On to turn on the Numlock key at bootup. The options are Off and On. CSM16 Module Version This item displays the version of CSM (Content Switch Module) currently used in the system. Gate20 Active If Upon Request is selected, Gate20 can be disabled via BIOS. Select Always to keep Gate20 always active when executing any RT (Register Transfer) Code above 1 MB. The options are Always and Upon Request. Option ROM Message Use this feature to select the Option ROM mode setting. The options are Force BIOS and Keep Current. Interrupt 19 Capture Interrupt 19 is the software interrupt that handles boot disk functions. When this item is set to Enabled, the ROM BIOS of the host adaptors will "capture" Interrupt 19 at bootup and allow the drives that are attached to these host adaptors to function as bootable disks. If this item is set to Disabled, the ROM BIOS of the host adaptors will not capture Interrupt 19, and the drives attached to these adaptors will not function as bootable devices. The options are Enabled and Disabled. 5-30 Chapter 4: AMI BIOS Boot Option Priorities Boot Option#1/Boot Option#2 Use this item to set the system boot sequence. If Built-in EFI (Extensible Firmware Interface) Shell is selected, the Built-in EFI Shell will become the first component to boot. The default setting for Boot Option #1 is Built-in EFI Shell, and for Option#2 is Windows Boot Manager. 5-8 Security Use this section to configure the privilege level of the user when accessing the system or the Setup Utility. Administrator Password If "Administrator Password" is selected for the system, the user can use an administrator password to enter the BIOS Setup Utility. No password will be needed for the user to enter the system at bootup. User Password If "User Password" is selected for the system, a password is needed for a user to enter the system and the BIOS Setup Utility at bootup. While in the BIOS Setup Utility, the user is granted with "Administrator Rights" and is allowed to change configuration settings in the Setup Utility. 5-31 X8OBN-F Platform User's Manual 5-9 Save & Exit Use this section to configure Save & Exit settings. Save Changes and Exit When you have completed the system configuration changes, select this feature and press <Yes> in the dialog box to save the changes you've made and reboot the system. After system reboot, the new system settings will take effect. Discard Changes and Exit Select this feature and press <Yes> in the dialog box to quit the BIOS Setup without making any permanent changes to the system configuration settings. Save Changes and Reset Select this feature and press <Yes> in the dialog box to save all the changes you've made and reset the system. Discard Changes and Reset Select this feature and press <Yes> in the dialog box to discard all the changes and reboot the system. Save Options Save Changes Select this feature and press <Yes> in the dialog box to save any changes you've made and reboot the system. 5-32 Chapter 4: AMI BIOS Discard Changes Select Discard Changes and press <Yes> in the dialog box to discard any changes you've made and return to the Setup Utility. Restore Defaults Select this feature and press <Yes> in the dialog box for the AMI BIOS to automatically load Optimal Defaults to the BIOS Settings. The Optimal settings are designed for maximum system performance, but they may not work best for some computer applications. Save as User Defaults Select this feature and press <Yes> in the dialog box for the AMI BIOS to save the defaults that you've selected as "User Defaults" for future use. Restore User Defaults Select this feature and press <Yes> in the dialog box for the AMI BIOS to restore user default settings that you had previously saved. Boot Override Built-in EFI Shell Select this feature and press <Yes> in the dialog box for the AMI BIOS to save the changes you've made on the Built-in EFI Shell settings and reboot the system. Windows Boot Manager Select this feature and press <Yes> in the dialog box for the AMI BIOS to save the changes you've made on the Windows Boot Manger settings and reboot the system. 5-33 X8OBN-F Platform User's Manual Note 5-34 Appendix A: BIOS POST Error Codes Appendix A BIOS Error Beep Codes During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the bootup process. The error messages normally appear on the screen. Fatal errors will not allow the system to continue to bootup. If a fatal error occurs, you should consult with your system manufacturer for possible repairs. These fatal errors are usually communicated through a series of audible beeps. The numbers on the fatal error list correspond to the number of beeps for the corresponding error. A-1 BIOS Error Beep Codes BIOS Error Beep Codes Beep Code/LED Error Message Description 1 beep Refresh Circuits have been reset. (Ready to power up) 5 short beeps + 1 long beep Memory error No memory detected in the system 8 beeps Display memory read/write error Video adapter missing or with faulty memory OH LED On System OH System Overheat A-1 X8OBN-F Platform User's Manual Notes A-2 Appendix B: Software Installation Instructions Appendix B Software Installation Instructions B-1 Installing Software Programs After you've installed the operating system, a screen as shown below will appear. You are ready to install software programs and drivers that have not yet been installed. To install these programs, click the icons to the right of these items. Note: To install the Windows OS, please refer to the instructions posted on our Website at http://www.supermicro.com/support/manuals/. Driver/Tool Installation Display Screen Note 1. Click the icons showing a hand writing on the paper to view the readme files for each item. Click on a computer icon to the right of an item to install this item (from top to the bottom), one at a time. After installing each item, you must reboot the system before proceeding with the next item on the list. The bottom icon with a CD on it allows you to view the entire contents of the CD. Note 2. When making a storage driver diskette by booting into a Driver CD, please set the SATA Configuration to "Compatible Mode" and configure SATA as IDE in the BIOS Setup. After making the driver diskette, be sure to change the SATA settings back to your original settings. B-1 X8OBN-F Platform User's Manual B-2 Configuring SuperDoctor III The SuperDoctor III program is a Web-based management tool that supports remote management capability. It includes Remote and Local Management tools. The local management is called the SD III Client. The SuperDoctor III program included on the CDROM that came with your baseboard allows you to monitor the environment and operations of your system. SuperDoctor III displays crucial system information such as CPU temperature, system voltages and fan status. See the Figure below for a display of the SuperDoctor III interface. Note: 1 The default user name and password are ADMIN. Note 2: In the Windows OS environment, the SuperDoctor III settings take precedence over the BIOS settings. When first installed, SuperDoctor III adopts the temperature threshold settings previously set in BIOS. Any subsequent changes to these thresholds must be made within SuperDoctor, since the SD III settings override the BIOS settings. For the Windows OS to adopt the BIOS temperature threshold settings, please change the SDIII settings to be the same as those set in BIOS. SuperDoctor III Interface Display Screen-I (Health Information) B-2 Appendix B: Software Installation Instructions SuperDoctor III Interface Display Screen-II (Remote Control) Note: SD III Software and the user's guide can be downloaded from our Website at: http://www.supermicro.com/products/accessories/software/ SuperDoctorIII.cfm. For Linux, we will still recommend that you use SuperDoctor II. B-3 X8OBN-F Platform User's Manual Notes B-4 (Disclaimer Continued) The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment, nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency communication devices or other critical systems whose failure to perform be reasonably expected to result in significant injury or loss of life or catastrophic property damage. Accordingly, Supermicro disclaims any and all liability, and should buyer use or sell such products for use in such ultra-hazardous applications, it does so entirely at its own risk. Furthermore, buyer agrees to fully indemnify, defend and hold Supermicro harmless for and against any and all claims, demands, actions, litigation, and proceedings of any kind arising out of or related to such ultra-hazardous use or sale.