Download MELSEC-Q Programming/Structured

S.VLMT1
9.18
S.VLMT1
Variation Rate Limiter 1
9.18
S.VLMT1
Ladder diagram
Start contact
S.VLMT1
S.VLMT1
S1
S2
D1
Structured ladder/FBD
D2
Structured text language
S_VLMT1
EN
Input argument
Output argument
Setting
d1
s2
d2
Bit
ENO:=S_VLMT1(EN,s1,s2,d1,d2);
EN
: Execution condition
: Bit
S1
: Input data start device
: Real data type
: Array of real data type (0..3)
S2
: Operation constant start device
ENO
: Execution result
: Bit
D1
: Block memory start device
: Array of any 16-bit data (0..2)
D2
: Dummy device*1
: Real data type
Internal devices
data
ENO
s1
Word
R, ZR
J
Bit
\
U
Word
Zn
\G
S1
––
––
D1
––
––
S2
––
––
D2
––
––
*1
Constant
Special register SD1506 can be specified as a dummy device.
Function
Limits the varying speed of the output value.
Input
Input
Hysteresis
Hysteresis
t
Output
1
0
t
BB1
BW
Output
1
0
BB2
BW
t
(Positive Direction)
168
(Negative Direction)
t
Other