Download PC7457

Completion Unit
Branch Processing Unit
Fetcher
BTIC (128-Entry)
CTR
BHT (2048-Entry)
LR
SRs
(Shadow)
128-Entry
ITLB
Dispatch
Unit
Data MMU
96-Bit (3 Instructions)
SRs
(Original)
VR Issue
(4-Entry/2-Issue)
GPR Issue
(6-Entry/3-Issue)
FPR Issue
(2-Entry/1-Issue)
Completes up
to three
instructions
per clock
Reservation
v
Stations (2)
VR File
16 Rename
Buffers
Reservation Reservation
Reservation Reservation
v
Station
Station
Station
Station
Vector
Integer
er
Unit 1
Vector
FPU
Reservation
Reservation
Reservation
Station
Station
Station
Integer
Unit 2
Integer
Integer
Integer
Unit
Unit
Unit122
(3)
x÷
+++
32-Bit
128-Bit
Vector
Touch
Queue
GPR File
16 Rename
Buffers
32-Kbyte
Tags D Cache
128-Entry
DTLB
DBAT Array
Reservation
Stations (2-Entry)
Vector
Integer
er
Unit 2
32-Kbyte
I Cache
Tags
IBAT Array
Completion Queue
(16-Entry)
Vector
Permute
Unit
128-Bit (4 Instructions)
Instruction MMU
EA
Load/Store Unit
Vector Touch Engine
PA
+ (EA Calculation)
Finished
Stores
Reservation
Stations (2)
FPR File
L1 Castout
16 Rename
Buffers
FloatingPoint Unit
L1 Push
32-Bit
32-Bit
Completed
Stores
PC7457 Microprocessor Block Diagram
- Time Base Counter/Decrementer
- Clock Multiplier
- JTAG/COP Interface
- Thermal/Power Management
- Performance Monitor
Instruction Queue
(12-Word)
1. Block Diagram
Instruction Unit
Figure 1-1.
e2v semiconductors SAS 2007
Additional Features
+ x÷
FPSCR
Load Miss
64-Bit
64-Bit
128-Bit
Memory Subsystem
L1 Store Queue
(LSQ)
L1 Load Queue (LLQ)
L1 Service
Queues
512-Kbyte UniÞed L2 Cache Controller
Line Block 0 (32-Byte) Block 1 (32-Byte)
Tags Status
Status
L3 Cache Controller(1)
Line Block 0/1
Tags Status
Load
Queue (11)
L3CR
L2 Prefetch (3)
Instruction Fetch (2)
Cacheable Store Request(1)
L2 Store Queue (L2SQ)
Snoop Push/
L1 Castouts
Interventions
(4)
Notes: 1. The L3 cache interface is not implemented on the PC7447.
2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries.
The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
Bus Accumulator
19-Bit Address
64-Bit Data
(8-Bit Parity)
External SRAM
(1, 2, or 4 Mbytes)
Bus Store Queue
Castout
Queue (9)/
Push
Queue (10)(2)
Bus Accumulator
36-Bit
Address Bus
64-Bit
Data Bus
3
PC7457
0827E–HIREL–03/07
L1 Load Miss (5)
System Bus Interface