Download SN32F100 Spec.

SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
Bit
Name
31:8
Reserved
7
RXFIFOTHIF
6
TXFIFOTHIF
5
RXFIFOUDIF
4
TXFIFOOVIF
3:0
Reserved
Description
RX FIFO threshold interrupt flag
0: No RX FIFO threshold interrupt
1: RX FIFO threshold triggered.
TX FIFO threshold interrupt flag
0: No TX FIFO threshold interrupt
1: TX FIFO threshold triggered.
RX FIFO underflow interrupt flag
0: No RX FIFO underflow
1: RX FIFO underflow (RX FIFO is empty and still being read).
TX FIFO overflow interrupt flag
0: No TX FIFO overflow
1: TX FIFO overflow (TX FIFO is full and still being written).
Attribute
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Attribute
Reset
R
0
W
0
W
0
W
0
W
0
R
0
Attribute
Reset
R
0
Attribute
Reset
W
0
13.6.6 I2S Interrupt Clear register (I2S_IC)
Address Offset: 0x14
Bit
Name
31:8
Reserved
7
RXFIFOTHIC
6
TXFIFOTHIC
5
RXFIFOUDIC
4
TXFIFOOVIC
3:0
Reserved
Description
0: No effect
1: Clear RXFIFOTHIF bit
0: No effect
1: Clear TXFIFOTHIF bit
0: No effect
1: Clear RXFIFOOUDIF bit
0: No effect
1: Clear TXFIFOOVIF bit
13.6.7 I2S RX FIFO register (I2S_RXFIFO)
Address Offset: 0x18
Bit
Name
31:0
RXFIFO[31:0]
Description
8 x 32-bit RX FIFO
13.6.8 I2S TX FIFO register (I2S_TXFIFO)
Address Offset: 0x1C
Bit
Name
31:0
TXFIFO[31:0]
13.7
Description
8 x 32-bit TX FIFO
CODEC ADC REGISTERS
Base Address: 0x4006 4000

Note: Codec ADC Registers are available only when codec mode is selected by I2SMOD=1.
13.7.1 ADC Setting 1 register (ADC_SET1)
Address Offset: 0x540
Bit
31:8
Name
Reserved
SONiX TECHNOLOGY CO., LTD
Description
Page 143
Attribute
R
Reset
0
Version 1.4