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r------- -------------- V F 0 -------- ---- --------,
FDC internal
clock
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SYNC signal-+----------<p-----t------------,
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R D A T A--+----.----I
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CONTROL CIRCUIT
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r------Gain switch signal
,----...1--...1...-----,
Compensates for
frequency difference
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------------------~
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Regulated voltage:
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Compensates for phase difference
HWINDOW
PLLI
CIRCUIT
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WIN DOW - ; - - - - - - - - . - 4
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Divider
WINDOW
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~-------------------------------------Constant
voltage
source
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----t
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REGULATOR
CIRCUIT
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~--------------------
Figure 7-1.
86 HITACHI
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_____________________ J
VFO Circuit Block Diagram