Download Developer`s Kit XC167CI

Developer's Kit XC167CI
6.9. Clock Generation
The external clock input range refers to a CPU clock range of 1...40 MHz.
Besides, the PLL usage is limited to a 4-50MHz input frequency range. All
configurations need a crystal to generate the CPU clock through the internal
oscillator amplifier, except the Direct Drive mode (oscillator amplifier disabled, so
no crystal or resonator can be used). Vice versa, the clock can be forced
through an external clock source only in Direct Drive mode.
Table 7: Selection of CPU clock
P0H.7
P0H.6
P0H.5
CPU-Clock
fPLL = fOSC * F
External Clock Input fOSC
Range in MHz (1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fOSC * 0.5
fOSC * 2.5
fOSC * 2.5
fOSC * 1
fOSC * 5
fOSC * 2
fOSC * 4.5
fOSC * 3
4 - 50
12 - 16
8 - 12
4 - 40
4-6
12.5 -18.7
5.6 - 8.3
8.3 - 12.5
(1) The Developer’s Kit XC161CI comes with an external 5 MHz quartz. The CLKCFG
pins are set by default to a factor of 5 (CPU internal = 25 MHz !).
XC167CI_UMa.doc
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