Download User`s Manual EPIA-PX

Chapter 3
DRAM CLOCK/DRIVE CONTROL
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock / Drive Control
DRAM Clock
DRAM Timing
x SDRAM CAS Latency [DDR/DDR
x Bank Interleave
x Precharge to Active(Trp)
x Active to Precharge(Tras)
x Active to CMD(Trcd)
x REF to ACT/REF (Trfc)
x ACT(0) to ACT(1) (TRRD)
Read to Precharge (Trtp)
Write to read CMD (Twtr)
Write Recovery Time (Twr)
DRAM Command Rate
RDSAIT mode
x RDSAIT selection
: Move
Enter: Select
F5: Previous Values
[By SPD]
[Auto By SPD]
2.5 / 4
Disabled
4T
07T
4T
25T
3T
[2T]
[1T/2T]
[4T]
[2T Command]
[Auto]
03
+/-/PU/PD: Value
F10: Save
F6: Fail-Safe Defaults
Item Help
Menu Level
ESC: Exit
F1: General Help
F7: Optimized Defaults
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [By SPD, 100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz, 333MHz
DRAM Timing
The value in this field depends on the memory modules installed in your
system. Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, Auto By SPD]
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