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Transcript
Section 4
Interfaces of the COM
49
USB 2.0 Controller #3 - Can be configured to use regular USB 2.0 port 2 (USB2). This controller shares the
same USB 2.0 port 2 pins with the XUSB controller.
4.16.1
Signals
Table 51: USB signals
Signal
USB0_D_N
USB0_D_P
USB0_ID
USB0_VBUS
USB_VBUS_EN0_nOC
USB1_D_N
USB1_D_P
USB_VBUS_EN1_nOC
USB2_D_N
USB2_D_P
USB_VBUS_EN2_nOC
USB3_RX0_N
Pin
X2:53
X2:55
X2:57
X2:59
X3:36
X3:28
X3:30
X3:34
X3:18
X3:16
X3:54
X3:9
USB3_RX0_P
X3:7
USB3_TX0_N
X3:1
USB3_TX0_P
X3:3
PEX_USB3_RX1_N
X3:19
PEX_USB3_RX1_P
X3:21
PEX_USB3_TX1_N
X3:13
PEX_USB3_TX1_P
X3:15
Description
USB0 (OTG) data
USB0 (OTG) data
USB0 (OTG) ID
USB0 (OTG) VBUS
USB0 enable/overcurrent
USB1 data
USB1 data
USB1 enable/overcurrent
USB2 data
USB2 data
USB2 enable/overcurrent
USB 3.0 receive data lane
(negative). Shared with
PCIe.
USB 3.0 receive data lane
(positive). Shared with
PCIe.
USB 3.0 transmit data
lane (negative). Shared
with PCIe.
USB 3.0 transmit data
lane (positive). Shared
with PCIe.
USB 3.0 receive data lane
(negative). Shared with
PCIe.
USB 3.0 receive data lane
(positive). Shared with
PCIe.
USB 3.0 transmit data
lane (negative). Shared
with PCIe.
USB 3.0 transmit data
lane (positive). Shared
with PCIe.
I/O
I/O
I/O
I
P
I
I/O
I/O
I
I/O
I/O
I
I
Comment
requires pull-up against 3.3V
requires pull-up against 3.3V
requires pull-up against 3.3V
I
O
O
I
I
O
O
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