Download Tegra K1 Embedded Platform Design Guide

Tegra K1 Embedded Platform
Design Guide
3.0 Interface Routing Guidelines
3.1 Overview
This section contains the PCB routing and other guidelines for the following Tegra interfaces
Clocks
DRAM
USB
PCIe
SATA
HSIC
DSI
LVDS
eDP
HDMI
CSI
DTV
Note:
SDMMC
I2S
I2C
SPI
UART
JTAG
Strapping Pins
Thermal Diode
Unless otherwise noted, all resistor values are ±5% & trace impedance values are ±15%
Signal Name Conventions
The following conventions are used in describing the signals for Tegra:


Signal names use a mnemonic to represent the function of the signal (i.e. Secure Digital Interface #3 CMD
signal is SDMMC3_CMD), written in bold to distinguish it from other text. Active low signals usually have
an underscore followed by capital N (_N) after the name (i.e. SYS_RESET_N). Differential signals are
identified as a pair with the same names that end with _P and _N or just P and N (for positive and
negative, respectively). For example, USB1_DP and USB1_DN indicate a differential signal pair.
I/O Type The signal I/O type is represented as a code to indicate the operational characteristics of the
signal. The table below lists the I/O codes used in the signal description tables.
Table 12. Signal Type Codes
Code
Definition
A
Analog
DIFF I/O
Bidirectional Differential Input/Output
DIFF IN
Differential Input
DIFF OUT
Differential Output
I/O
Bidirectional Input/Output
I
Input
O
Output
OD
Open Drain Output
I/OD
Bidirectional Input / Open Drain Output
P
Power
General SFIO (Special Function IO) & GPIO (General Purpose IO) selection.

The SFIO and GPIO usage should match those used on Jetson TK1, or alternative “Use-case” options shown
in the Jetson TK1 Pinmux spreadsheet.
Tegra | K1 | DG-07508-001v03 | Copyright © 2014, 2015 NVIDIA Corporation. All rights reserved.
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