Download VAX MP Technical Overview

spinning in OpenVMS loop, and hence is not checking for the changes in SCH$GL_IDLE_CPUS.
Therefore, when SCH$GL_IDLE_CPUS is changed by OpenVMS by clearing the bits for VCPUs that
are currently hibernated by VAX MP in idle sleep state, these VCPUs must be woken up out of
sleep state so they can recheck the value of SCH$GL_IDLE_CPUS and respond to its change.
To restate, clearing bits in SCH$GL_IDLE_CPUS should cause VCPUs with corresponding CPU IDs
be woken out of sleep state.
To implement this, when VSMP kernel-resident module is being loaded into VMS kernel, it
reports virtual address of SCH$GL_IDLE_CPUS to SIMH layer of VAX MP. Reported address is
stored by VAX MP in variable sys_idle_cpu_mask_va. VAX MP then monitors changes to this
virtual address, i.e. to SCH$GL_IDLE_CPUS. To reduce overhead of this monitoring, it is
performed only within the implementation of those VAX instructions that OpenVMS actually
uses to clear bits in SCH$GL_IDLE_CPUS: CLRL, BICL2, BBSC. When VAX MP detects that any of
these instructions had changed SCH$GL_IDLE_CPUS, VAX MP will wake up VCPUs with CPU IDs
corresponding to cleared bits out of idle sleep.
sys_idle_cpu_mask_va is reset by VAX MP on operating system shutdown or primary processor
reset. Care is also taken to temporary disable its handling while processor is interrupted to
console ROM firmware via CTRL/P or BREAK and to resume it on CONTNUE from console ROM.
•
Milliseconds as a unit of time measurement had been replaced by microseconds, wherever
available, to provide a greater accuracy of current CPU speed calibration and forward progress
calculation after idle sleep.
•
SIMH dynamically calibrates virtual processor execution speed to provide a conversion from
milliseconds to the number of instruction cycles. This conversion is used to create event queue
entries scheduled in terms of time domain, but tracked in terms of VCPU instruction cycles
remaining till the event should be processed. SIMH adjusts calibration data every second. VAX
MP modifies SIMH VCPU speed calibration algorithm by averaging calibration data across all the
active VCPUs. When performing the averaging, VAX MP takes into the account calibration data
only for those VCPUs that had been sufficiently active during last one-second cycle. Data for
those VCPUs that spend virtually all time of their last cycle in idle sleep (rather than executing) is
not used for averaging, since its precision can be poor and distort the average.
•
XQ handler was modified to issue appropriate memory barriers (smp_mb and smp_wmb) when
accessing BDL.
•
MSCP controller handlers (RQ and TQ) were modified to issue appropriate memory barriers
(smp_mb and smp_wmb) when accessing UQSSP COMM area.
143