Download VAX MP Technical Overview

Per-unit registers described by UDATA_GBL have loctype set to REG_LOCTYPE_GBL_UNIT and
are accessed with accessor method sim_reg::getloc_unit_idx(RUN_DECL, uint32
unit_index) whenever indexing is required.
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Macros that define backing store location of virtual registers (HRDATA, DRDATA, ORDATA,
FLDATA, GRDATA, BRDATA) had been split into two versions: xxDATA_GBL defines location
for registers shared by all CPU units, xxDATA_CPU defines location of per-CPU registers private
to each processor.
For BRDATA registers, BRDATA_CPU used together with BRDATA_CPU_QPTR additionally
define a per-cpu location for qptr field. Methods sim_reg::getqptr and
sim_reg::setqptr had been provided to access qptr regardless of the kind of baking store in
use.
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Virtual device interrupt raising and dispatching mechanics has been revised to support
multiprocessor environment.
Some IO devices in the initial release of VAX MP normally do not have threads of their own and
their implementation code executes in the thread context of one virtual processor or another,
i.e. the context of the worker thread for some virtual processor. Other devices do have worker
threads associated with them and can send interrupts from these threads (although in most
cases they signal the completion of IO operation to the part of SIMH handler executing in the
context of primary VCPU and performs post-processing there, such as queuing device event
entries, before sending an interrupt to VAX level).
Accordingly there are several scenarios for raising interrupts in VAX MP:
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When a per-CPU device raises an interrupt, this happens in the context of the thread
executing the device’s owning processor. In this case processor’s thread sends the
interrupt to the current processor.
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Interrupts from system-wide (not per-CPU) devices are handled, by design, by the
primary CPU (CPU0). 135 When a system-wide device raises an interrupt, the device can
be executing in the context of any virtual processor in the system (unless guest OS
affinity mask “pins” device to a particular virtual processor or processors), leading to this
processor’s thread sending an interrupt to the CPU0. Thus, when system-wide device
raises an interrupt, it can be sent from the execution context of any processor to CPU0.
See discussion in section “Dispatching device interrupts” above.
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