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Download DMC-18x6 - Galil Motion Control
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Read FIFO Count N+6 to N+7 Read Only 9 bits starting at N+6 contain the number of characters currently in the read FIFO (0 to 511) Write FIFO Count N+10 to N+11 Read Only 9 bits starting at N+10 contain the number of characters currently in the write FIFO (0 to 511) Simplified Communication Procedure The simplest approach for communicating with the DMC-18x6 is to check bits 0 and 2 of the CONTROL register at address N+4. Bit 0 is for WRITE STATUS and bit 2 is for READ STATUS. Read Procedure - To receive data from the DMC-18x6, read the control register at address N+4 and check bit 2. If bit 2 is zero, the DMC-18x6 has data to be read in the READ register at address N. Bit 2 must be checked for every character read. Write Procedure - To send data to the DMC-18x6, read the control register at address N+4 and check bit 0. If bit 0 is zero, the DMC-18x6 FIFO buffer is not full and a character may be written to the WRITE register at address N. If bit 0 is one, the buffer is full and any additional data will be lost. Any high-level computer language such as C, Basic, Pascal or Assembly may be used to communicate with the DMC18x6 as long as the READ/WRITE procedure is followed as described above, so long as the base address is known. FIFO Control Register at N+4 Status Bit Read/Write Meaning 7 Read Only If 1, DPRAM empty 6 Read/Write IRQ enable: Write 1 to enable IRQ Write 0 to disable IRQ Read 1 = IRQ enabled 5 Read/Write IRQ status: Write 1 to clear IRQ Read 1 = IRQ pending 4 Read/Write Freeze Status of DPRAM: Write 1 to freeze DPRAM Write 0 to clear freeze of DPRAM Read 1 = DPRAM frozen 3 Read Only If 1, DPRAM is busy updating 2 Read Only If 1, DMC to PC Buffer empty, No data to be read 1 Read Only If 0, PC to DMC buffer not half full. Can write at least 255 bytes. If 1, buffer is more than half full. 0 Read Only If 1, PC to DMC Buffer full, Do not write data Half Full Flag The Half Full flag (Bit 1 of the control register) can be used to increase the speed of writing large blocks of data to the controller. When the half full bit is zero, the write buffer is less than half full. In this case, up to 255 bytes can be written to the controller at address N without checking the buffer full status (bit 0 of the control register). Reading the Data Record from the DPRAM Immediate access to any or all bytes of the data record is available by reading from the Dual Port RAM registers. The starting address for the dual port RAM is stored at BAR0 of the PCI configuration space. The memory map below describes the data record registers and the associated controller information. The following procedure for “freezing” the data record (DPRAM) should be followed to ensure that all data of the data record is from the same sample period: DMC-18x6 Chapter 4 Software Tools and Communications • 55
