Download LPC32x0

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ARM_CLK
ARM Clock — Based on the HCLK PLL output, SYSCLK, or PERIPH_CLK.
Clock switching and HCLK PLL settings give ARM_CLK a very wide range of
potential frequencies
Used by: ARM9 CPU, MSSDCLK.
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Description
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Clock Name
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Clocks and clock usage
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LPC32x0
Chapter 4: LPC32x0 Clocking and power control
Table 6.
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NXP Semiconductors
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Used by: the AHB matrix and USB AHB, AHB slaves, FAB slaves, and APB
slaves.
PERIPH_CLK
Peripheral Clock — Based on SYSCLK or HCLK PLL output divided by 1 to
32. The maximum supported frequency of PERIPH_CLK is 20 MHz, typically
13 MHz.
Typically, the PERIPH_CLK divider setting is chosen such that the
PERIPH_CLK frequency remains the same when switching from Direct RUN
mode to RUN mode, taking into account the HCLK PLL settings. This case
occurs when the PERIPH_CLK frequency equals the SYSCLK frequency in
RUN Mode.
Used by: Many peripheral functions.
clk48mhz
USB 48 MHz clock — Based on OSC_CLK.
The USB interface must be run from a 48 MHz clock. The USB specification
has strict requirements for frequency (500 ppm) and jitter (500 ps). For this
reason, the crystal-based OSC_CLK is used as the source for this clock, and
must be running while the USB is active. OSC_CLK is divided by n before it
enters the USB PLL, which must multiply the frequency up to 48 MHz when
the USB is to be used.
Used by: USB block.
DDRAM_CLK
DDR SDRAM Clock — Based on the HCLK PLL output or SYSCLK, divided
by 1 or 2.
If DDR SDRAM is used, this clock must be programmed to be twice the HCLK
frequency. In RUN mode this is typically the same as the ARM_CLK
frequency, but there is support for ARM clocking 4 times as fast as HCLK as
well. In Direct RUN mode, it is not possible to generate this clock, so DDR
SDRAM cannot be accessed in Direct RUN mode.
Used by: EMC controller.
MSSDCLK
SD Card Clock — Based on ARM_CLK, divided by 1 to 15.
The Main oscillator and the RTC oscillator are shown at the lower left of the diagram. To
the right of the Main oscillator may be found the clock mode logic, governed by the Start
Controller. To the right of the clock mode logic is the HCLK PLL, clock switching logic and
clock dividers, which provide clocks to most of the chip. Certain peripherals that are partly
clocked by the RTC clock are shown at the lower right of Figure 4–6, while the USB block
and its special clocking logic are shown at the top.
<Document ID>
User manual
© NXP B.V. 2008. All rights reserved.
Rev. 00.26 — 20 November 2008
40 of 719
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The AHB HCLK will typically be ARM_CLK divided by 2 but can run at the
same frequency as the ARM or be divided by 4. The AHB HCLK frequency
should not be set higher than 104 MHz or lower than SYSCLK.
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AHB Bus Clock — Based on PERIPH_CLK, SYSCLK, or HCLK PLL output
divided by 1, 2, or 4.
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HCLK