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UM10211
NXP Semiconductors
Chapter 13: LPC2300 USB device
USBReEp |= (UInt32) ((0x1 << endpt));
/* Load Endpoint index Reg with physical endpoint no.*/
USBEpIn = (UInt32) endpointnumber;
/* load the max packet size Register */
USBEpMaxPSize = MPS;
/* check whether the EP_RLZED bit in the Device Interrupt Status register is set
*/
while (!(USBDevIntSt & EP_RLZED))
{
/* wait until endpoint realization is complete */
}
/* Clear the EP_RLZED bit */
Clear EP_RLZED bit in USBDevIntSt;
}
The device will not respond to any transactions to unrealized endpoints. The SIE
Configure Device command will only cause realized and enabled endpoints to respond to
transactions. For details see Table 13–294.
8.5.3 USB Endpoint Index register (USBEpIn - 0xFFE0 C248)
Each endpoint has a register carrying the MaxPacketSize value for that endpoint. This is
in fact a register array. Hence before writing, this register is addressed through the
USBEpIn register.
The USBEpIn register will hold the physical endpoint number. Writing to USBMaxPSize
will set the array element pointed to by USBEpIn. USBEpIn is a write only register.
Table 264. USB Endpoint Index register (USBEpIn - address 0xFFE0 C248) bit description
Bit
Symbol
Description
Reset value
4:0
PHY_EP
Physical endpoint number (0-31)
0
31:5
-
Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
8.5.4 USB MaxPacketSize register (USBMaxPSize - 0xFFE0 C24C)
On reset, the control endpoint is assigned the maximum packet size of 8 bytes. Other
endpoints are assigned 0. Modifying USBMaxPSize will cause the endpoint buffer
addresses within the EP_RAM to be recalculated. This is a multi-cycle process. At the
end, the EP_RLZED bit will be set in USBDevIntSt (Table 13–243). USBMaxPSize array
indexing is shown in Figure 13–51. USBMaxPSize is a read/write register.
Table 265. USB MaxPacketSize register (USBMaxPSize - address 0xFFE0 C24C) bit
description
Bit
Symbol
Description
Reset value
9:0
MPS
The maximum packet size value.
0x008[1]
31:10 [1]
Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0.
UM10211_1
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 6 July 2007
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