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XMC1100 XMC1000 Family Debug System (DBG) SCS_DCRSR Debug Core Register Selector Register (DF4H) 31 15 30 14 29 13 28 12 27 26 11 10 25 9 24 23 Reset Value: 0000 0000H 22 21 20 19 18 17 16 0 REG WnR r rw 8 7 6 5 4 3 2 1 0 REGSEL r rw 0 Field Bits Type Description REGSEL [4:0] rw REGSEL - Specifies the ARM core register or special-purpose register to transfer 00000B- 01100B ARM core register R0-R12. For example, 0b00000 specifies R0 and 0b00101 specifies R5 01101B The current SP. See also values 0b10001 and 0b10010. 01110B LR. 01111B Debug Return Address. 10000B xPSR. 10001B Main stack pointer, MSP. 10010B Process stack pointer, PSP. 10100B Bits[31:24] Control; Bits[23:8] Reserved; Bits[7:0] PRIMASK. In each field, the valid bits are packed with leading zeros. For example DCRDR [31L26] is 0b00000. REGWnR 16 rw REGWnR specifies the type of access for the transfer read. 0B 1B write. 0 [31:17] r , [15:5] Reference Manual DEBUG, V3.1 Reserved 20-28 V1.0, 2013-03 Subject to Agreement on the Use of Product Information
