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XMC1100 XMC1000 Family Universal Serial Interface Channel (USIC) PSR Protocol Status Register [ASC Mode] (48H) 31 30 29 28 13 14 AIF RIF TBIF TSIF DLIF RSIF rwh rwh rwh 11 26 15 rwh 12 27 rwh 10 rwh 25 9 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 0 BRG IF r rwh 8 7 6 5 4 3 2 1 0 FER FER RXID TXID BUS RNS COL SBD TFF RFF Y 1 0 LE LE r rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description TXIDLE 0 rwh Transmission Idle This bit shows if the transmit line (DX1) has been idle. A frame transmission can only be started if TXIDLE is set. The transmitter line has not yet been idle. 0B The transmitter line has been idle and frame 1B transmission is possible. RXIDLE 1 rwh Reception Idle This bit shows if the receive line (DX0) has been idle. A frame reception can only be started if RXIDLE is set. 0B The receiver line has not yet been idle. The receiver line has been idle and frame reception 1B is possible. SBD 2 rwh Synchronization Break Detected1) This bit is set if a programmed number of consecutive bit values with level 0 has been detected (called synchronization break, e.g. in a LIN bus system). A synchronization break has not yet been detected. 0B A synchronization break has been detected. 1B COL 3 rwh Collision Detected1) This bit is set if a collision has been detected (with PCR.CDEN = 1). 0B A collision has not yet been detected and frame transmission is possible. A collision has been detected and frame 1B transmission is not possible. Reference Manual USIC, V2.10 14-69 V1.0, 2013-03 Subject to Agreement on the Use of Product Information
