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DE2-70 User Manual 5.8 Using the 24-bit Audio CODEC The DE2-70 board provides high-quality 24-bit audio via the Wolfson WM8731 audio CODEC ( udio l/DECoder). This chip supports microphone-in, line-in, and line-out ports, with a sample rate adjustable from 8 kHz to 96 kHz. The WM8731 is controlled by a serial I2C bus interface, which is connected to pins on the Cyclone II FPGA. A schematic diagram of the audio circuitry is shown in Figure 5.14, and the FPGA pin assignments are listed in Table 5.12. Detailed information for using the WM8731 codec is available in its datasheet, which can be found on the manufacturer’s web site, or in the Datasheet/Audio CODEC folder on the DE2-70 System CD-ROM. 1u C39 1u R99 4.7K R100 4.7K 5 2 4 1 3 C38 LINE IN NCL R NCR L GND J11 PHONE JACK B VCC33 VCC33 R108 R109 2K 2K R101 R102 4.7K 4.7K AGND AGND J10 21 20 19 18 17 16 15 R104 C41 680 10u AGND C42 R105 1n 47K AGND A_VCC33 J12 LINE OUT AGND AGND AGND NCL R NCR L GND EXPOSED DACDAT DACLRCK ADCD AT ADCLRCK HPVDD LHPOUT RHPOUT WM8731 MBIAS VMID AGND AVDD ROUT LOUT HPGND 5 2 4 1 3 XTI/MCLK XTO DCVDD DGND DBVDD CLKOUT BCLK PHONE JACK P PHONE JACK G 29 8 9 10 11 12 13 14 1 2 3 4 5 6 7 AUD_XCK AUD_BCLK AUD_DACDAT AUD_DACLRCK AUD_ADCD AT AUD_ADCLRCK 1u SCLK SDIN CSB MODE LLINEIN RLINEIN MICIN U13 A_VCC33 AGND C40 28 27 26 25 24 23 22 I2C ADDRESS READ IS 0x34 I2C ADDRESS WRITE IS 0x35 MIC IN 330 NCL R NCR L GND R103 5 2 4 1 3 I2C_SDAT I2C_SCLK AGND AGND C43 100u C44 A_VCC33 100u R106 R107 47K 47K AGND AGND Figure 5.14. Audio CODEC schematic. Signal Name FPGA Pin No. Description AUD_ADCLRCK PIN_F19 Audio CODEC ADC LR Clock AUD_ADCDAT PIN_E19 Audio CODEC ADC Data AUD_DACLRCK PIN_G18 Audio CODEC DAC LR Clock AUD_DACDAT PIN_F18 Audio CODEC DAC Data AUD_XCK PIN_D17 Audio CODEC Chip Clock AUD_BCLK PIN_E17 Audio CODEC Bit-Stream Clock I2C_SCLK PIN_J18 I2C Data I2C_SDAT PIN_H18 I2C Clock Table 5.12. Audio CODEC pin assignments. 48 AGND
