Download HI5905EVAL2 User Guide

Application Note 9785
correction logic uses the supplementary bits to correct any
error that may exist before generating the final fourteen-bit
digital data output (D0-D14) of the converter.
φ1
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is presented on
the digital data output bus on the 4th cycle of the clock after
the analog sample is taken. This delay is specified as the
data latency. After the data latency time, the data
representing each succeeding analog sample is output on
the following clock pulse. The output data is synchronized to
the external sampling clock with a data latch and is
presented in offset binary format.
φ1
VIN +
CS
φ2
VIN -
φ1
φ1
CH
VOUT +
+
VOUT -
CS
CH
φ1
φ1
FIGURE 17. ANALOG INPUT SAMPLE-AND-HOLD
ANALOG
INPUT
CLOCK
INPUT
SN-1
HN-1
HN
SN
SN+1
HN+1
SN+2
HN+2
SN+3
HN+3
SN+4
HN+4
SN+5
HN+5
SN+6
HN+6
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N-1
B2, N-2
3RD
STAGE
4TH
STAGE
B1, N
B2, N-1
B3, N-2
B4, N-3
5TH
STAGE
DATA
OUTPUT
B1, N+1
B2, N
B3, N-1
B4, N-2
B1, N+2
B2, N+1
B3, N
B4, N-1
B2, N+2
B3, N+1
B4, N
B5, N-3
B5, N-2
B5, N-1
DN-4
DN-3
DN-2
B1, N+3
B2, N+3
B3, N+2
B4, N+1
B5, N
DN-1
B5, N+1
DN
NOTES:
1. SN: N-th sampling period.
2. HN: N-th holding period.
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
FIGURE 18. HI5905 INTERNAL CIRCUIT TIMING
B1, N+5
B2, N+4
B3, N+3
B4, N+2
tLAT
3-14
B1, N+4
B3, N+4
B4, N+3
B5, N+2
B5, N+3
DN+1
DN+2