Download Multi-Channel High Speed Counter

4-26
Configuration and Programming
C/R(n): Count or Rate Value Bit
(Words 1 to 4, Bit 08)
These bits are only used when the module is configured for Class 1
operation. Depending on the operating mode, the module only
transmits the counter’s count or rate value. The count value is
transmitted when the C/R(n) bit is reset. The rate value is transmitted
when the C/R(n) bit is set. When configured for Class 4, setting these
bits generates a programming error.
P(n): Program Counter (n) Bit
(Words 1 to 4, Bit 15)
If this bit is reset, bits 1 to 14 must be zero or a programming error
results. This bit must be set before the counter control bits are
updated for the counter. This allows the user to write 0000H into
unused words in the block without inadvertently changing the state of
a counter. When this bit is zero, all other bit values in the word are
retained inside the module. This affects the soft preset, SP(n), as
described in the note on page 4-25.
Output ON (OR) Mask
(Word 5, Bits 00 to 07)
This is a bit pattern which allows the user program to globally turn on
outputs, regardless of the programmed ranges and Enable Ranges
bytes. When a bit in this byte is zero, the output will turn on based on
the programmed ranges, the state of the enable ranges byte, and
Output Enable Mask. When this bit is one, the output is on if the
corresponding bit in the Output Enable Mask equals one.
Output Enable Mask
(Word 5, Bits 08 to 15)
This is a bit pattern to globally turn off outputs, regardless of the
programmed ranges and enable ranges bytes. When a bit in this mask
is zero, the output is off regardless of the programmed ranges and the
state of the Output ON Mask. When a bit in this mask is one, the
Publication 1746-UM002B-EN-P - August 2004