Download UM10732 LPC11U6x/E6x User manual

UM10732
NXP Semiconductors
Chapter 22: LPC11U6x/E6x Windowed Watchdog Timer (WWDT)
Table 335. Watchdog operating modes selection
WDEN WDRESET Mode of Operation
0
X (0 or 1)
Debug/Operate without the Watchdog running.
1
0
Watchdog interrupt mode: the watchdog warning interrupt will be generated
but watchdog reset will not.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated.
1
1
Watchdog reset mode: both the watchdog interrupt and watchdog reset are
enabled.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated, and the watchdog counter reaching zero
will reset the microcontroller. A watchdog feed prior to reaching the value of
WDWINDOW will also cause a watchdog reset.
22.5.2 Watchdog Timer Constant register
The TC register determines the time-out value. Every time a feed sequence occurs the
value in the TC is loaded into the Watchdog timer. The TC resets to 0x00 00FF. Writing a
value below 0xFF will cause 0x00 00FF to be loaded into the TC. Thus the minimum
time-out interval is TWDCLK  256  4.
If the WDPROTECT bit in WDMOD = 1, an attempt to change the value of TC before the
watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a
watchdog reset and set the WDTOF flag.
Table 336. Watchdog Timer Constant register (TC, 0x4000 4004) bit description
Bit
Symbol Description
Reset
Value
23:0
COUNT Watchdog time-out value.
0x00 00FF
31:24 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
22.5.3 Watchdog Feed register
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors.
After writing 0xAA to WDFEED, access to any Watchdog register other than writing 0x55
to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled, and sets
the WDTOF flag. The reset will be generated during the second PCLK following an
incorrect access to a Watchdog register during a feed sequence.
It is good practise to disable interrupts around a feed sequence, if the application is such
that some/any interrupt might result in rescheduling processor control away from the
current task in the middle of the feed, and then lead to some other access to the WDT
before control is returned to the interrupted task.
UM10732
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 4 March 2014
© NXP B.V. 2014. All rights reserved.
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