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Download TX System RISC TX79 Core Architecture (Symmetric 2
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Appendix A CPU Instruction Set Details DADDU 31 DADDU Doubleword Add Unsigned 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DADDU 101101 6 5 5 5 5 6 MIPS III Format: DADDU rd, rs, rt Purpose: To add 64-bit integers. Description: rd ← rs + rt The 64-bit doubleword value in GPR rt is added to the 64-bit value in GPR rs and the 64bit arithmetic result is placed into GPR rd. No Integer Overflow exception occurs under any circumstances. Restrictions: None Operation: GPR[rd] 63..0 ← GPR[rs] 63..0 + GPR[rt] 63..0 Exception: None Programming Notes: The term “unsigned” in the instruction name is a misnomer; this operation is 64-bit modulo arithmetic that does not trap on overflow. It is appropriate for arithmetic which is not signed, such as address arithmetic, or integer arithmetic environments that ignore overflow, such as C language arithmetic. A-37
