Download Volume 6, Issue 2 - Verification Academy

his experiences in “Using SystemVerilog Packages in Real Verification
Projects.” You’ll find some really useful recommendations on how best
to use packages to organize your code to make it easier to reuse and
share. The article concludes with an interesting discussion of how
to use classes and packages together to achieve some very useful
results.
Our friends at XtremeEDA follow up their “Agile Transformation in IC
Development” article from our February 2010 issue with the other side
of the coin in “Agile Transformation in Functional Verification.” In part
one, they lay out a feature-based approach to verification planning,
with emphasis on prioritization and incremental planning. In our next
issue, they’ll share some practical results from an actual project.
For those of you who have been “banging on the countertops” about
formal verification, our next article by our colleague Harry Foster will
show you that it’s “Time to Adopt Formal Property Checking.” Harry
gives three reasons that it is indeed the right time to adopt, and gives
you a straightforward 7-step process for getting started. With the
technology maturing to the point where you don’t need to be a formal
expert, there’s really no reason not to check it out.
Our next article is “Simulation-Based FlexRayTM Conformance
Testing – an OVM success story” from our partner Verilab. Here we
see a good example of OVM’s flexibility being used to implement
multiple levels of abstraction in a constrained-random environment.
Their work was used as part of the FlexRay Consortium effort to
produce a SystemC executable model and a conformance test
specification – all made possible by OVM and some knowledgeable
folks at Verilab.
In “Multi-method Verification of SoC Designs in an OVM Testbench,”
a team takes you through many of the issues you’ll encounter in
verifying a typical SoC design, in this case using the AMBA interconnect with multiple peripherals and one or more CPU cores.
The article shows, once again, how OVM serves as a verification
platform that enables block-to-top reuse of verification infrastructure,
including pre-packaged interface-specific VIP in the form of Questa
Multi-view Verification Components (MVCs). You’ll also see how this
infrastructure enables you to adopt formal property checking using
assertions built into the MVCs and also provides the flexibility to use
Intelligent Testbench Automation and ultimately software running
on the processor model to augment the stimulus and coverage of
your verification efforts. Another example of combining different
“instruments” in perfect harmony!
We next take a more in-depth look at MVCs in “Reusable OVM
Sequences Boost Verification Productivity” and “Faster Verification
and Debugging Using an MVC at Multiple Abstraction Levels.” First we
show you the advantages of some sequence extensions provided by
MVCs, enabling you to write sequences at a higher level of abstraction,
and how to use the existing OVM infrastructure to control which
sequence runs on a particular MVC. The second article shows how the
MVC makes it easier to debug at the transaction level and plan your
verification efforts to ensure protocol compliance.
Our Partners’ Corner section, as always, includes several articles
from our Questa Vanguard partners. We continue the discussion of
debugging with “Accelerated Debug: A Case Study” from our friends
at Vennsa Technologies. This article provides an example of their new
OnPoint automated debugging tool running in concert with Mentor’s
0-In to quickly diagnose the cause of failing assertions. Next, we find
PSI Electronics showing us how they accomplished “Verification of
a Complex IP Using OVM and Questa: From Testplan Creation to
Verification Success.”
2
Our final Partners’ Corner article lets you take advantage of
the excellent insight John Aynsley of Doulos offers in “Making OVM
Easier for HDL Users.” This article includes some practical rules and
guidelines to help those of you in the “HDL designer” community
enter the wonderful world of OVM.
We close this issue with a collaboration between Mentor’s
Emulation Division and our friends at ARM in “Accelerating Software
Debug Using ARM’s VSTREAM with Veloce™ Hardware Emulation.”
This article shows Veloce’s TestBench XPress technology, TBX,
being used with ARM’s VSTREAM debug transactor to connect a
software debugger directly to an ARM-based design in the same way
the debugger can be used with Questa, but with the much greater
performance you’d expect from using an emulator.
Now I know you’re wondering how David and Megan managed
to pull off a concert from two different rooms on two different floors.
Fortunately, David’s drums were loud enough that Megan could hear
them downstairs. For David to hear Megan, they used our walkietalkies! Megan’s was broadcasting from the piano and David had
his up in his room so he could hear the piano. The concert was a
smashing success – it even brought a tear to their mom’s eye.
I couldn’t have been a prouder dad.
Have a great DAC, and be sure to drop by the Mentor booth
to say hello.
Respectfully submitted,
Tom Fitzpatrick
Verification Technologist
Mentor Graphics