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Download Xilinx System Generator for DSP User Guide (UG640)
Transcript
Black Box Examples 8. Drag and drop the black box from the "Basic Elements" library in the coregen_import_example2.mdl. Select fir_compiler_8tap_wrapper.vhd for the top-level HDL file. 9. Connect the black box to the open wires. 10. Open the fir_compiler_8tap_wrapper_config.m file, and add the VHDL file, EDIF netlist and MIF files to the black box file list as shown below. These files get included as part of the System Generator netlist for the design when it is generated. Note: The order in which the files are added in the configuration function is the order in which they get compiled during synthesis and simulation. System Generator for DSP User Guide UG640 (v 14.3) October 16, 2012 www.xilinx.com 369
