Download Longitudinal ADC / DAC User Manual - Diagnostic

B. ADC LEDs
The ADC VME board has 3 LEDs which visualise the status of
the board. The 3 LEDs are denoted as X, Y and Z.
LED
X
Color
off
green
red
Y
Z
yellow
off
green
red
yellow
off
green
red
yellow
X Y Z
Description
Should never happen. Check power or hardware
defect.
The clock system in the FPGA is working properly.
Due to the implementation of the clock system this
indicates that the RF clock jitter is less than 150ps and
no RF clock period was missed.
The clock system in the FPGA is NOT working
properly. Due to the implementation of the clock
system this indicates that the RF clock jitter was/is
bigger than 150ps and/or RF clock period was missed.
Not implemented.
Currently no VME access to this card.
VME signalling access.
VME signalling acknowledge.
Both of the above.
VME Commute directing ADC data to ZBT RAM buffer
and FPDP interface.
VME Commute directing ADC data to FPDP interface
only.
VME Commute directing ZBT RAM buffer data to
FPDP interface (a debugging feature).
VME Commute directing ADC data to ZBT RAM buffer
only.
C. Registers and functionality
1. Address 0x000000 (Status Register)
a) 21: DVALID
The FPDP bus transmits the DVALID bit set.
b) 0: 125 MHz Clock Lock
This bit is set if the clocks are working according to the specs of the DCM
(Digital Clock Manager) inside the FPGA. For more information on the
DCM please refer to the XILINX datasheet of the VirtexII FPGA.
2. Address 0x000010 (Control Register)
a) 31:Board Reset
A write access at this bit causes:
o Stop of any running acquisition.
o Reset the FPDP interface.
Paul Scherrer Institut • 5232 Villigen PSI
MBFB_ADC_DAC_User_Manual.doc/ 12/13/06 /page 6 of 29