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areas). In order to model the control flow we make use of CPS matrices. Component
Power State (CPS) matrices capture the power state for all the components in each
cycle. For example, consider a design that contains k different types of components
(C_1,...,C_k) with n_i components of type i. If the design has the latency of T cycles,
then k two dimensional matrices are constructed where the i-th matrix is of size Txn_i.
An entry in a CPS matrix represents the power state of a component during a specific
cycle and is determined by the algorithm (Figure 38).
Figure 37: Libray of components
However, specification of such a matrix is not easy. Hence, we take advantage of the
typical loop oriented structures of kernels such as matrix multiply, FFT, etc. for which
the FPGA based designs are created. If we analyze the CPS matrices, we can observe
that another easy way to specify the same information is through a table. Such table
would contain a number of rows where each row is a 3-tuple (component, state, #of
cycles in this state). As we are interested only in performance estimation, this much of
information is enough.
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