Download SECTION 4 CENTRAL PROCESSOR UNIT

DECODE
BUFFER
STAGE
C
STAGE
B
STAGE
A
INSTRUCTION PIPELINE
CONTROL STORE
PROGRAM
COUNTER
SECTION
DATA
SECTION
CONTROL LOGIC
EXECUTION UNIT
MICROSEQUENCER AND CONTROL
WRITE PENDING
BUFFER
PREFETCH
CONTROLLER
MICROBUS
CONTROLLER
ADDRESS
BUS
BUS CONTROL
SIGNALS
DATA
BUS
1127A
Figure 4-1 CPU32 Block Diagram
4.2 CPU32 Registers
The CPU32 programming model consists of two groups of registers that correspond
to the user and supervisor privilege levels. User programs can use only the registers
of the user model. The supervisor programming model, which supplements the user
programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of the
MC68010 and later processors.
The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit
program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status
register, two alternate function code registers, and a 32-bit vector base register. Refer
to Figure 4-2 and Figure 4-3.
MC68332
USER’S MANUAL
CENTRAL PROCESSOR UNIT
Rev. 15 Oct 2000
MOTOROLA
4-2