Download Élan™SC520 Microcontroller Register Set Manual

GP DMA Controller Registers
GP-DMA Channel 3 Extended Page (GPDMAEXTPG3)
7
6
4
3
0
0
2
0
0
0
0
RSV
R/W
1
0
DMA3ADR[27–24]
Reserved
Bit
Reset
5
Memory-Mapped
MMCR Offset D89h
0
0
R/W!
Register Description
This register provides the extended page address for Channel 3.
Bit Definitions
Bit
Name
Function
7–4
Reserved
Reserved
This bit field should be written to 0 for normal system operation.
3–0
DMA3ADR
[27–24]
DMA Channel 3 Extended Page Address
This bit field specifies the highest four memory address bits (A27–A24) for Channel 3.
Programming Notes
The extended page address is used in conjunction with the memory address and the page address registers for the
associated channel to make up a 28-bit address (A27–A0).
In enhanced mode, the Channel 3 extended page address bit field (DMA3ADR[27–24]) increments or decrements
if the memory address crosses the 16-Mbyte boundary. In normal mode, these bits remain constant during the DMA
transfer.
Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4).
Élan™SC520 Microcontroller Register Set Manual
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