Download Élan™SC520 Microcontroller Register Set Manual

Programmable Interval Timer Registers
Direct-Mapped
PIT 0 Status (PIT0STA)
I/O Address 0040h
PIT 1 Status (PIT1STA)
I/O Address 0041h
PIT 2 Status (PIT2STA)
I/O Address 0042h
Bit
7
6
OUTPUT
NULL_CNT
Reset
0
0
R/W
R
R
5
4
3
RW[1–0]
0
2
1
CTR_MODE_STA[2–0]
0
0
R
0
R
0
BCD
0
0
R
Register Description
These registers contain the programmed mode and the null count value for each timer channel.
Bit Definitions
Bit
7
Name
Function
OUTPUT
Output State
Output signal state for the timer channel. Each timer channel has an output that is driven
High or Low based on the current mode. See the CTR_MODE_STA bit description on
page 13-6 for a list of modes.
0 = Output is Low.
1 = Output is High.
The three PIT outputs can be mapped individually to the microcontroller’s internal
programmable interrupt controller inputs. In addition, the PIT Channel 2 output can be
enabled to drive the PITOUT2 pin. See the PIT_OUT2_ENB bit description on
page 13-13.
6
NULL_CNT
Null Count
When programming a new count value into one of the timers, the new value does not
take effect until it has actually been transferred to the counting element, which can take
some time. When attempting to read back a count value, software can test this bit to
determine whether the read-back value is valid or not.
0 = Counter is available for reading.
1 = Null count; read-back of the counter is invalid.
5–4
RW[1–0]
Counter Read/Write Operation Control or Counter Latch Command
Reflects the last bit setting that was programmed into the corresponding bits (5–4) of the
PITMODECTL or PITCNTLAT register for this PIT channel (see page 13-7 and
page 13-10).
00 = Counter Latch command (PITCNTLAT register).
01 = Read/write counter bits 7–0 only (PITMODECTL register).
10 = Read/write counter bits 15–8 only (PITMODECTL register).
11 = Read/write counter bits 7–0 followed immediately by bits 15–8
(PITMODECTL register).
Élan™SC520 Microcontroller Register Set Manual
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