Download SNIDS: FPGA-based Implementation of a Simple Network Intrusion

Verilog
templates
Set of Strings
Verilog module
generator
Bit-split FSM
automatic
generator
Tiles
Rule_Modules
(Verilog)
Memory
initalization
files (COE)
BRAM
description
COREGEN
Top level
modules
(Verilog)
BRAM
Netlist
Pcore
Synthesis
Figure 9: Automatic SNIDS generator
had to generate a separate Verilog module for each rule module and each tile within each module.
For this purpose, we implemented shell scripts that create a number of Verilog files named rule module X,
where X varies from one to the total number of modules, as well as the files tile X Y, Y = 1, . . . , 4 for each
rule module X. These files are generated by modifying specific template Verilog sources that we wrote. Each
module tile X Y instantiates the corresponding BRAM module state table X Y. This module serves as the
wrapper for the BRAM netlist generated by the CoreGen.
The top-level modules instantiate the rule modules, the connecting logic, and the OPB snooping frontend. Together with the above mentioned automatically generated files, they are given as input to the EDK
environment, which is then used to produce the synthesizable SNIDS core. The details of the files and the
directory structure used to implement the SNIDS core in XPS are described in Appendix A.
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