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APPEB1003 User’s Manual, Rev. 1.0, February 2003
cap-XX
PC Card Extender
and Supercapacitor
Evaluation Board
Part No. APPEB1003
User’s Manual
Revision 1.0
February, 2003
Evaluation Board
Features
•
•
•
•
•
PC Card Extender
Supercapacitor (two form factors)
Adjustable current limit circuit with Supercapacitor charge enable
3.3V and 5V input LEDs
Supercapacitor voltage comparator with adjustable
threshold, adjustable hysteresis and Power Good LED
• Card Detect switches to simulate card removal and insertion
• Sub-circuits can be disconnected to reduce the load
• Test points, jumpers and I/O connectors
Typical Supercapacitor
Applications
•
•
•
•
•
•
•
PC Card
Compact Flash
PDA
Smartphone
GPRS
Handheld Equipment
Load Leveling
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
Contents
1.0
Introduction
3
2.0
Input Voltage
3
2.1 Charge Time
3
3.0
Current Limit
4
4.0
Enable
4
5.0
Power Good
4
6.0
Adjusting the Circuit
5
6.1 Adjusting Hysterisis Width with “PGOOD Feedback” - R23
6.2 Adjusting the High Threshold with “PGOOD Reference” - R15
6.3 Adjusting the Current Limit with “Current Limit” - R2
6.4 Replacing the Potentiometers with Fixed Resistors
6.5 Limits of Adjustment
6
6
7
7
8
Connecting the Evaluation Board
8
7.1 VCC Modes
7.2 Current Measurement
7.3 Card Detect
7.4 Voltage Select
9
10
11
11
Disconnecting Circuits for Reduced Load
11
7.0
8.0
Appendix
Schematic
PCB Top Overlay
PCB Top Layer
PCB 2nd Layer
PCB 3rd Layer
PCB Bottom Layer
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
1.0 Introduction
This User’s Manual is for the cap-XX PC Card Extender and Supercapacitor Evaluation
Board (Part No. APPEB1003). This board was designed for the evaluation of a
supercapacitor in a PC Card. The application of supercapacitors is limited only by the
user’s imagination. Typical examples are PC Card, Compact Flash, PDA, Smartphone,
GPRS and other handheld equipment.
The Evaluation Board is basically a PC Card Extender with a supercapacitor and a
current limit circuit.
An excellent source for information on Supercapacitors and free downloads are
available on the cap-XX website at www.cap-xx.com.
In the following description of operation it may be helpful to refer to the Evaluation
Board Schematic in the Appendix.
2.0 Input Voltage
The supercapacitors for the Evaluation Board are rated at 4.5V and therefore it is not
recommended that the input voltage (VCC) be greater than 4.5V. If VCC is 5V then the
Equivalent Series Resistance rise rate of the supercapacitor is increased and the
lifetime will be reduced. A red LED is included to indicate that VCC is too high and it
starts to glow when VCC is approximately 4.2V. The red LED is labeled on the
Evaluation Board as “5 Volts”. If VCC is 5V then the voltage can be dropped to < 4.5V
by including an external series diode in the voltage supply lines on the Evaluation
Board (see section 7.0). A yellow LED is included to indicate when VCC is 3.3V or
greater. It is labeled on the Evaluation Board as “3.3 Volts”.
If VCC is disconnected (or if the Evaluation Board is removed from the host) and
there is still charge on the supercapacitor then current will flow through the body
diode of M1 and through the yellow LED (also through the red LED if the
supercapacitor is greater than ~ 4.2V). The intensity of the yellow LED then gives an
indication of the voltage remaining on the supercapacitor. If, however, external
series diodes have been included to reduce the 5V rail to 4.5V then the LEDs will not
be ON when VCC is disconnected.
2.1 Charge Time
A fully discharged supercapacitor will be charged to VCC after a certain time (tc). This
time will depend on the current limit (IL), VCC and the capacitance (C). The equation
is
tc =
© cap-XX Pty Ltd, 2003
CVCC
IL
(1)
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
3.0 Current Limit
Circuits that employ large capacitors generally need a current limiting circuit to
alleviate the current in-rush problem. The PC Card specification states that for 3.3V
the peak current is 1000mA and the average current is 750mA. For 5V the peak
current is 660mA and the average current is 500mA. Therefore the peak power from
either the 3.3V rail or the 5V rail is 3.3W and the average power is 2.5W. The
Evaluation Board has an adjustable current limit circuit. The current limit can be
adjusted from 0A to ~ 4.5A by using the potentiometer R2. It is labeled on the
Evaluation Board as “Current Limit”. Turning the potentiometer clockwise will
increase the current limit.
The MOSFET (M1) and Sense Resistor (R1) can withstand up to 4.5A whilst the
supercapacitor is being charged. They cannot however withstand the 4.5A
indefinitely. Also, there is no short circuit protection. The MOSFET (M1) has a
maximum average power dissipation of 2.5W. Therefore any continuous load
resistance (RL) has a minimum value as given by equation 2.
RL >
VCC I L − 2.5
(2)
I 2L
4.0 Enable
The current limit circuit has an enable feature. Enable is an active low signal and the
two pin jumper is labeled on the Evaluation Board as “J_ENABLE”. It is an input
signal to the Evaluation Board and it can be jumpered to ground, to be permanently
enabled, or it can be externally driven by an open collector or drain. When
“J_ENABLE” is externally driven it allows the supercapacitor to be charged only when
the User’s Card is ready. Pin 2 of “J_ENABLE” is the control input and Pin 1 is
permanently connected to ground.
5.0 Power Good
The Power Good circuit (PGOOD) is included to indicate when the supercapacitor is
charged to the appropriate level. The voltage on the supercapacitor is compared to a
reference using a comparator with adjustable thresholds and hysteresis. The
thresholds need to be adjustable on an Evaluation Board because different
applications will require different load voltages. The hysteresis also needs to be
adjustable because a step in load current will cause a step voltage on the
supercapacitor because of the supercapacitor’s Equivalent Series Resistance (ESR).
Since this step voltage (part of the ripple) is a normal occurrence, it would not be
desirable for this to indicate that the supercapacitor is undercharged.
Power
Good
LED On
LED Off
VTL
VW
Vcc
VTH
Figure 1 Power Good Hysteresis
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
As in Figure 1, the high threshold (VTH) is the voltage at which the supercapacitor’s
unloaded voltage becomes acceptable. The hysteresis (VW) is the voltage that when
subtracted from the high threshold gives the low threshold (VTL). It indicates that the
supercapacitor is undercharged. VTH is set by the factory at 3.2V and VW is set at
0.3V, therefore VTL is 2.9V.
PGOOD has a header labeled on the Evaluation Board as “H_PGOOD”. It is an active
high output signal that can be used to signal an external circuit that the
supercapacitor is fully charged. A green LED is also included to indicate this
condition. It is labeled on the Evaluation Board as “Power Good”.
6.0 Adjusting the Circuit
Equipment needed: Adjustable power supply, multi-meter and various power
resistors
Warning: Be careful not to exceed the supercapacitor rated voltage (4.5V) or the
maximum average power rating for M1 (2.5W)
Sections 6.1, 6.2 and 6.3 explain how to adjust the circuit practically and section 6.4
gives the theoretical equations.
(a) Connect a load power resistor (RL) of around 10Ω from “VCC_OUT” to
“GND_OUT” on “CON_CAPXX”. This ensures that the supercapacitor
voltage will change in reasonable time when the power supply voltage is
changed. Note the power rating of RL has to be a minimum value
according to equation 3.
PR L >
VCC _ OUT 2
RL
(3)
(b) Ensure the following jumpers are fitted; “J_RED&YLW”, “J_GREEN”,
“J_PGOOD”, “J_ENABLE”, “J_VCC17_IN” (pins 3 and 4), “J_VCC51_IN”
(pins 3 and 4), “J_VPP18” and “J_VPP52” .
(c) Turn the “Current Limit” - R2 fully clockwise (maximum current).
(d) Turn the “PGOOD Reference” - R15 to around mid position (about 11 turns
from either limit).
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
6.1 Adjusting Hysteresis Width with “PGOOD Feedback” - R23
NOTE: VW is adjusted before VTH because the VTH adjustment is affected by VW.
Therefore if adjustments are made in this section then section 6.2 should be
checked.
(a) Decide the high threshold voltage VTH , the low threshold voltage VTL and
the hysteresis voltage width VW (Vw = VTH - VTL). VTL has to be greater
than the minimum voltage required by the Pulsed Load. VW has to be
greater than the expected voltage droop due to the ESR and capacitor
discharge etc.
(b) Set the power supply voltage to say 3.3VDC. Ensure that the power supply
can supply the desired current. Connect its negative lead to J_GND1 or
J_GND2. Connect the positive lead to pin 1 of J_VCC17_IN or
J_VCC51_IN. The LED labeled “3.3 Volts” should now be ON and the LED
labeled “Power Good” should also be ON. If “Power Good” is not ON, then
turn “PGOOD Reference” - R15 anticlockwise slowly until the “Power Good”
LED is ON.
(c) Connect a voltmeter across the supercapacitor, which is also across RL and
“CON_CAPXX” ( VR L ). Slowly reduce the power supply voltage and note
VR L when the “Power Good” LED turns OFF. Slowly increase the power
supply voltage and note VR L when the “Power Good” LED turns ON. The
difference between the two readings is the hysteresis voltage width Vw.
(d) Adjust “PGOOD Feedback” - R23 (anti-clockwise increases Vw) and repeat
(c) above until precisely the desired hysteresis width is achieved.
6.2 Adjusting the High Threshold with “PGOOD Reference” - R15
(a) Turn “PGOOD Reference” - R15 fully clockwise and then reduce the power
supply voltage until the “Power Good” LED is OFF.
(b) Adjust the power supply voltage so VR L equals the desired VTH. Turn
“PGOOD Reference” - R15 slowly anti-clockwise until the “Power Good”
LED turns ON.
(c) Check that the “Power Good” LED turns ON and OFF at the desired levels.
This can be done by varying the power supply voltage in both directions
so that VR L is less than VTL and then greater than VTH.
(d) Remove RL.
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
6.3 Adjusting the Current Limit with “Current Limit” - R2
Warning: the maximum average power rating for M1 is 2.5W (see section 3.0)
(a) Connect a load resistor to “CON_CAPXX” (RL) that draws just over the
desired current limit from the PC Card host. Note the power rating of the
resistor is according to equation 3 and RL has to be a minimum value
according to equation 2. For example if the supply voltage is 3.3V and the
desired current limit is 1A then an RL < 3.3 Ω would draw more than 1A.
According to equation 2, RL also has to be > 800mΩ. Choose say 2.7Ω
(next standard value < 3.3 Ω) and equation 3 says the power rating must
be greater than 4W.
(b) With an ammeter in series with the power supply, adjust “Current Limit” R2 until the current is limited to the desired value (clockwise increases the
current).
(c) Remove the load.
6.4 Replacing the Potentiometers with Fixed Resistors
The potentiometers on the Evaluation Board are included to provide flexibility in
evaluating many different applications. In a final design for production the resistance
of the potentiometers would have been decided and therefore they can be replaced
with fixed resistors. This section includes the equations that can be used to
theoretically determine the value of these resistors. The value of these resistors can
also be found practically by measuring the resistance of the potentiometers out of
circuit once the circuit has been successfully adjusted as above.
R 22 + R 23 =
55k
VW
(4)
R15 + R16 =
4k 7VTH
5 + VW − VTH
(5)
R2 =
© cap-XX Pty Ltd, 2003
22k
56
−1
IL
(6)
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
6.5 Limits of Adjustment
From the schematic in the Appendix it can be seen that;
R22=100kΩ
R23=500kΩ potentiometer
R15=5kΩ potentiometer
R16=3k9Ω
R2= 2kΩ potentiometer
From equation 4;
From equation 5;
From equation 6;
0.1V ≤ VW ≤ 0.5V
2.3V ≤ VTH ≤ 3.3V (VW=0.1V)
2.4V ≤ VTH ≤ 3.5V (VW=0.3V)
2.5V ≤ VTH ≤ 3.6V (VW=0.5V)
0A ≤ I L ≤ 4.7 A
If these limits do not suit the application then resistors can be replaced on the
Evaluation Board according to equations 4,5 and 6.
7.0 Connecting the Evaluation Board
The evaluation board is inserted into the Host and the PC Card under test is inserted
into the Evaluation Board, as shown in figure 2. The supercapacitor terminals are
joined to the connector labeled “CON_CAPXX”. The terminals of “CON_CAPXX” are
labeled “GND_OUT” and “VCC_OUT”. These are to be connected as close as possible
to the ground and positive supply of the Pulsed Load respectively. For the least
voltage droop, it is important to minimise the resistance between the supercapacitor
and its load. Therefore the wires from “CON_CAPXX” to the Pulsed Load should be
as short and as thick as practical.
Warning: As stated earlier, if VCC is chosen to be 5V then the voltage at the
supercapacitor must be dropped to < 4.5V by including an external series diode. If
only one of the two VCC rails is to be used (VCC is on both pins 17 and 51 of the PC
Card socket) then the diode can be placed between pins 3 and 4 of the VCC jumper
“J_VCC?_IN” (where ? is either 17 or 51). If both the VCC rails are to be used then
two diodes should be included. One is placed between pins 3 and 4 of “J_VCC17_IN”
and the other between pins 3 and 4 of “J_VCC51_IN”. Choose each diode such that
the minimum load current (quiescent current) gives an acceptable voltage drop. The
minimum load can be adjusted to some extent by the choice of supercapacitor
balancing resistors. The PC Card specification states that the 5V rail is ± 5% and
therefore the rail may be as high as 5.25V. In this case a voltage drop of 0.75V is
required. If the diode does not give enough voltage drop for the minimum current
case then two diodes in series may be needed. This is still more economical than
using a Low Drop Out (LDO) regulator.
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
Note: The number 1 pin of a header or jumper can be identified on the Evaluation
Board as the one with the square solder pad on the bottom layer.
PC Card Under Test
H
O
S
T
Other
Circuitry
Pulsed loads
(eg GPRS Module)
V+
GND
Figure 2 Typical connection of Evaluation Board
7.1 VCC Modes
Figure 2 shows the typical way for connecting the Evaluation Board. VCC on the PC
Card Under Test is generally supplied by one of two modes. Mode 1, being the most
common, is when VCC is supplied from “J_VCC17_OUT” and/or “J_VCC51_OUT” (via
the “J_PCCARD_HEADER” pins 17 and 51). These VCC rails supply all the circuitry on
the PC Card Under Test (“Other Circuitry”) except for the “Pulsed Loads (V+)”, which
is supplied by the supercapacitor with the external wires. In this mode VCC is
available to the “Other Circuitry” as soon as the PC Card Under Test is powered up,
whereas the supercapacitor supply to the “Pulsed Loads” is delayed by the charge up
time according to equation 1.
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
Mode 1 is accomplished by the following;
(a) Remove the jumpers on “J_VCC17_OUT” and “J_VCC51_OUT”.
(b) Connect external leads from pin 1 of “J_VCC17_IN” to pin 3 of
“J_VCC17_OUT” and from pin 1 of “J_VCC51_IN” to pin 3 of
“J_VCC51_OUT”.
Mode 2 is when the supercapacitor supplies both the VCC for the PC Card Under Test
(“Other Circuitry”) as well as the “Pulsed Loads”. In this mode all supplies are
delayed according to equation 1.
Mode 2 is accomplished by the following;
(a) Place jumpers on pins 1 and 2 of “J_VCC17_OUT” and pins 1 and 2 of
“J_VCC51_OUT”.
(b) Ensure the external wires are removed from “J_VCC17_IN”
“J_VCC17_OUT” and “J_VCC51_IN” to “J_VCC51_OUT”.
to
Connections common to both Mode 1 and 2 are;
(a) Connect external wires (thick and short) from “CON_CAPXX” to the
“Pulsed Loads” on the PC Card Under Test.
(b) Place jumpers on pins 3 and 4 of “J_VCC17_IN” and “J_VCC51_IN”.
Remember to use the series diodes in place of the jumpers if using the 5V
rail.
(c) Place jumpers on pins 1 and 2 of “J_VPP18”, “J_VPP52”, “J_RED&YLW”,
“J_ENABLE”, “J_PGOOD” and “J_GREEN”.
(d) Remove jumpers
“J_VCC51_OUT”.
on
“J_CVS1”,
“J_CVS2”,
“J_VCC17_OUT”
and
NOTE: Care must be taken, in which ever mode is chosen, so that the charge up
time of the supercapacitor does not affect the operation of any reset or power rail
monitoring circuitry etc. As described in section 4.0 and 5.0, the “J_ENABLE” and
“H_PGOOD” signals may need to be interfaced with the PC Card Under Test for
proper control.
7.2 Current Measurement
The input (Host) current from the VCC rails can be measured with a current probe
that is clamped over two external wire loops. One loop is connected between pins 3
and 4 on “J_VCC17_IN” and the other loop between pins 3 and 4 on “J_VCC51_IN”.
Likewise, the input current from the VPP rails can be measured using two external
wire loops between pins 1 and 2 on “J_VPP18” and pins 1 and 2 on “J_VPP52”. If a
current probe is not available then a sense resistor can be used in place of the wire
loops. The voltage dropped across the resistor divided by the value of the resistor
equals the current.
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
7.3 Card Detect
The correct insertion of a PC Card is detected when both pins 36 and 67 are
grounded. These pins are typically grounded on the PC Card Under Test. However,
the ground signal can also be replicated by using jumpers across pins 35 and 36 on
“J_Test2” and pins 67 and 68 on “J_Test2”. The removal and insertion of the card
can be simulated by depressing and releasing either of the two micro-switches
“SW_CCD1” or “SW_CCD2”.
7.4 Voltage Select
The PC Card Under Test chooses the VCC voltage rail using pin 43 (CVS1). If CVS1 is
grounded then a VCC of 3.3V is requested, if it is left floating then 5V is requested.
This signal can be replicated with “J_CVS1”. Placing a jumper on “J_CVS1” forces the
signal to ground and therefore requests 3.3V. “J_CVS2” is undefined and should be
left floating.
8.0 Disconnecting Circuits for Reduced Load
The minimum voltage on some loads may be critical. Any current that the Evaluation
Board uses contributes to the droop on the input voltage. If the droop becomes
excessive then some of the functions on the Evaluation Board can be disconnected
to save current and therefore increase the input voltage. The red and yellow LEDS
can be disconnected by removing the jumper “J_RED&YLW”. The green LED can be
disconnected by removing the jumper “J_GREEN”. The entire PGOOD circuit can be
disconnected by removing the jumper “J_PGOOD”.
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APPEB1003 User’s Manual, Rev. 1.0, February 2003
Appendix
Schematic
The supercapacitor and current limit circuit can be isolated by removing
the jumpers on J_VCC17_IN, J_VCC51_IN, J_VCC17_OUT and J_VCC51_OUT.
VCC_IN
1
TP6
D1
2
TP5
R2
2k
TEST POINT
22k
M1
SUD45P03-10
22m
TEST POINT
1
1
LM4041DIM3-1.2
10k
R3
10k
C2
C1
47n
R6
R7
R10
3
R5
39k
FDV302P
M3
U1A
1
CX1
3
+
R
VCC_IN
R11
BAT54J
470
D2
JUMPER1
TP3
TP4
TEST POINT
capxx
1
J_RED&Y LW
Y ellow_LED
Schottkys
1
5k
R15
Vcapxx
FDV301N
C4
47n
TEST POINT
R16
3k9
R17
22k
6
5
4
+
JUMPER1
VCC_IN
TS1852
Vr
J_Enable can have its jumper removed and can be driven
by an external open collector if desired.
J_ENABLE
Power Good Circuit.
If H_PGOOD is high then the supercap rail is good.
1
C3
100n
2
D8
R14
4k7
2
4
J_VCC17_IN
CON4
1 2 3 4
D5
ZRC250
2
2
1
-
R8
39k
470
+
3
H_CAPXX
R9
1
-
M2
TS1852
8
2
Vcapxx
R4
10k
47n
VCC_IN
22
1 2 3 4
CON4
J_VCC51_IN
R13
680
R1
VCC_IN
If VCC for the test card is needed before the supercap is charged up
then external leads can be connected from J_VCC17_IN and J_VCC51_IN
to J_VCC17_OUT and J_VCC51_OUT or directly onto the test card. The
jumpers on J_VCC17_OUT and J_VCC51_OUT should be removed in this case.
8
R20
22k
H_PGOOD
R19
7
1
U1B
VCC_IN
3
R12
D3
D4
3
BAT54J
1
500k
R22
2
BZX84C3V3
Red_LED
These spring loaded switches simulate
card removal and insertion.
If VCC17_IN and VCC51_IN are 5V then both the Red and Yellow
LEDs will be on. If they are 3.3V then only the Yellow LED will be on.
These LEDs will also be powered by the supercapacitor
through the body diode of the current limiting Mosfet (M1) when
VCC17_IN and VCC51_IN are disconnected.
The LEDs can also be disconnected (J_RED&YLW) so as to not load the circuit.
SW_CCD1#
Normally Closed
D2FL
R23
1
CON_CAPXX is to connect low resistance leads to the test card so there
is a low resistance path from the supercap to the load
(ie not through the 68 pin connector). In a final design the supercap
should be placed as close as possible to the high current pulsed load.
J_Test1
1
TP1
TEST POINT
2
1
1
2
Vw = width of hysteresis
Vh = high threshold
Vr = reference
2
JUMPER1
CON2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1
Linking all POWER GOOD grounds and then jumpering to common ground
allows the POWER GOOD circuit to be disconnected.
1 2 3
J_VCC17_OUT and J_VCC51_OUT can have their
and an external supply can be connected if
Alternatively, leads can be connected from
J_VCC17_IN and J_VCC51_IN to supply VCC to
before the supercap charges up.
1 2 3
J_VCC51_OUT
CON3
VCC51_IN
H_VPP18
PCcard_socket
J_CVS1
1
J_CVS2
1
2
JUMPER1
A jumper on J_CVS1 ensures 3.3V.
jumper removed
desired.
here to
the card
J_PCCARD_HEADER
JUMPER17
VCC17_IN
J_VPP18
2
JUMPER1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Using external leads, the board can be configured such that
it is a pure extender card with no extra
loading or circuitry
ie, all pins straight through (the ground pins cannot be isolated).
J_GND 1&2 are test points to safely
put the CRO ground aligator clip.
J_GND1
1
J_GND2
2
JUMPER1
1
2
JUMPER1
PCcard_header
2
JUMPER1
H_VPP52
1
J_VPP52
2
JUMPER1
1
2
JUMPER1
VPP jumpers allow current to be measured.
VPP headers allow the connection of leads to the card
for another source of power.
Title
Size
D
Date:
© cap-XX Pty Ltd, 2003
J_GREEN
JUMPER1
Vr = Vh/(Vw/2.5+2)
J_PGOOD
CON_CAPXX
GND
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE0#
CAD9
CAD11
CAD12
CAD14
CCBE1#
CPAR
CPERR#
CGNT#
CINT#
VCC17
VPP18
CCLK
CIRDY #
CCBE2#
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
RFU
CCLKRUN#
GND
GND
CCD1#
CAD2
CAD4
CAD6
RFU
CAD8
CAD10
CVS1
CAD13
CAD15
CAD16
RFU
CBLOCK#
CSTOP#
CDEVSEL#
VCC51
VPP52
CTRDY #
CFRAME#
CAD17
CAD19
CVS2
CRST#
CSERR#
CREQ#
CCBE3#
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD2#
GND
JUMPER1
BCX20
J_VCC17_OUT
CON3
J_Test2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
JUMPER17
J_PCCARD_SOCKET
2
Q1
4k7
CCD1# and CCD2# can simply be grounded with
jumpers across pins 1&2 and pins 33&34 on J2.
This corresponds to pins 35&36 and pins 67&68
respectively on J_PCcard_header.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
1
R21
TP2
TEST POINT
The intensity of the Yellow LED gives an indication
of the voltage on the supercap when VCC17_IN and VCC51_IN are disconnected.
Normally Closed
SW_CCD2#
D2FL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
D6
Green_LED
JUMPER1
R23 = 22k*2.5/Vw - R22
JUMPER1
220
D7
ZRC250
2
1
100k
D9
R18
470
2
680
PC Extender Card
Document Number
<Doc>
Tuesday , December 10, 2002
Rev
<Rev Code>
Sheet
1
of
1
12
www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB Top Overlay
© cap-XX Pty Ltd, 2003
13
www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB Top Layer
© cap-XX Pty Ltd, 2003
14
www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB 2nd Layer
© cap-XX Pty Ltd, 2003
15
www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB 3rd Layer
© cap-XX Pty Ltd, 2003
16
www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB Bottom Layer
© cap-XX Pty Ltd, 2003
17