Download MPC185UM: MPC185 Security Co

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Data Encryption Standard Execution Units (DEU)
0
1
2
3
4
5
6
7
8
63
Field
---
Halt
IFW
OFR
IE
ID
RD
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
Addr
DEU_1 0x0A028, DEU_2 0x0B028
Figure 4-14. DEU Status Register
Table 4-3 describes the DEU Status Register’s signals.
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Table 4-9. DEU Status Register Signals
Bits
Name
0-1
----
Reserved
2
Halt
Halt. Indicates that the DEU has halted due to an error.
0 DEU not halted
1 DEU halted
Note: Because the error causing the DEU to stop operating may be masked to the interrupt
status register, the status register is used to provide a second source of information
regarding errors preventing normal operation.
3
IFW
Input FIFO Writable. The controller uses this signal to determine if the DEU can accept the
next burst size block of data.
0 DEU Input FIFO not ready
1 DEU Input FIFO ready
Note: The MPC185 implements flow control to allow larger than FIFO sized blocks of data
to be processed with a single key/IV. The DEU signals to the crypto-channel that a “burst
size” amount of space is available in the FIFO. The documentation of this bit in the DEU
status register is to avoid confusing a user who may read this register in debug mode.
4
OFR
Output FIFO Readable. The controller uses this signal to determine if the DEU can source
the next burst size block of data.
0 DEU Output FIFO not ready
1 DEU Output FIFO ready
Note: The MPC185 implements flow control to allow larger than FIFO sized blocks of data
to be processed with a single key/IV. The DEU signals to the crypto-channel that a “burst
size” amount of data is available in the FIFO. The documentation of this bit in the DEU status
register is to avoid confusing a user who may read this register in debug mode.
5
Interrupt_Error
This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register (Section 7.1.4, “Interrupt Status Register”).
0 DEU is not signaling error
1 DEU is signaling error
6
Interrupt_Done This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register (Section 7.1.4, “Interrupt Status Register”).
0 DEU is not signaling done
1 DEU is signaling done
7
Reset_Done
8:63
----
Description
This status bit, when high, indicates that DEU has completed its reset sequence, as reflected
in the signal sampled by the appropriate crypto-channel.
0 Reset in progress
1 Reset done
Reserved
Chapter 4. Execution Units
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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