Download DSP56F802, 56F802

56F802 General Description
• Up to 30 MIPS operation at 60MHz core frequency
• 8K × 16-bit words (16KB) Program Flash
• Up to 40 MIPS operation at 80MHz core frequency
• 1K × 16-bit words (2KB) Program RAM
• DSP and MCU functionality in a unified,
C-efficient architecture
• 2K × 16-bit words (4KB) Data Flash
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• 2K × 16-bit words (4KB) Boot Flash
• 1K × 16-bit words (2KB) Data RAM
• JTAG/OnCETM port for debugging
• Hardware DO and REP loops
• On-chip relaxation oscillator
• 6-channel PWM Module with fault input
• 4 shared GPIO
• Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
• 32-pin LQFP Package
• Serial Communications Interface (SCI)
• Two General Purpose Quad Timers with 2 external
outputs
6
PWM Outputs
PWMA
Fault A0
RESET
VCAPC VDD
5
2
2
JTAG/
OnCE
Port
2
3
A/D1
A/D2
VREF
Quad Timer C
2
Quad Timer D
or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
SCI0
or
GPIO
•
Application-Specific
Memory &
Peripherals
Analog Reg
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
PAB
•
PLL
•
PDB
XDB2
•
•
CGDB
XAB1
XAB2
•
INTERRUPT
CONTROLS
16
COP/
Watchdog
VSSA
Low Voltage
Supervisor
Address
Generation
Unit
Program Controller
and
Hardware Looping Unit
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
2
Digital Reg
ADC
Interrupt
Controller
VSS* VDDA
3
•
•
IPBB
CONTROLS
16
Relaxation
Oscillator
.
16-Bit
56800
Core
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
IPBus Bridge
(IPBB)
DATA BUS [15:0]
*includes TCS pin which is reserved for factory use and is tied to VSS
56F802 Block Diagram
56F802 Technical Data, Rev. 9
Freescale Semiconductor
3