Download IBM PowerPC 403GB User`s Manual

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address (eg, an external memory controller may log the error).
Thus, the PowerPC Architecture provides for a mechanism by which the system software
can protect those areas of the address space that are mapped to sensitive devices,
guarding them from accesses that are not actually required by the program flow. Note that
for cachable storage, the Architecture specifically allows for the accessing of the entire
cache block containing the referenced storage, even in guarded storage.
2.9.2
Primarily due to the fact that there is no memory management unit (MMU) function on the
PPC403GB, it does not implement the concept of guarded storage. The PPC403GB does
allow speculative instruction fetches to be performed to all storage, whether cacheable or
non-cacheable. The PPC403GB does not perform out-of-order execution, thus speculative
loads are never executed. In order to guard against speculative instruction fetches to
sensitive devices, the system hardware and system software designers need to be aware of
a number of details regarding the PPC403GB implementation.
2.9.2.1
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Speculative Accesses on PPC403GB
Pre-Fetch Distance from an Unresolved Branch
The instruction pre-fetcher will speculatively fetch down the predicted branch path (either
taken or sequential). The maximum distance down an unresolved branch path that the
fetcher can access is 7 instructions (28 bytes). This corresponds to the unresolved branch in
the DCD stage of the instruction queue (see Section 2.6 on page 2-23 for discussion of the
instruction queue), with the next 3 instructions in IQ1-IQ3, and the Instruction Cache Unit
(ICU) requesting the 4th subsequent instruction, which is at the start of a cache line
containing the 4th-7th instructions, all of which get accessed if the address is cachable. If
the address is non-cachable (as controlled by the ICCR), then only the 1st - 4th instructions
get accessed.
2.9.2.2
Pre-Fetch of Branch to Count / Branch to Link
When predicting that a Branch to the CTR or a Branch to the LR (bctr / blr) instruction will
be taken, the fetcher will not attempt to access the address contained in the CTR/LR if there
is a CTR/LR updating instruction ahead of the branch in the instruction queue, up to DCD
(see Section 2.6 for discussion of the instruction queue). In such a case, the fetcher
recognizes that the CTR/LR contains “wrong” data, which could be some random value
leftover from a previous use of the CTR/LR, and could likely be pointing to an invalid
address or an I/O device. In these cases, the fetcher will wait for the CTR/LR updating
instruction to enter EXE, at which time the “correct” CTR/LR contents are known, and the
fetcher can use this value in the prediction. In this manner, the fetcher can be prevented
from speculatively accessing a completely “random” address. The fetcher will only access
up to 7 instructions down the sequential path past an unresolved branch or down the taken
path of a relative or absolute branch, or at the contents of the CTR/LR when the CTR/LR
contents are known to be correct.
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PPC403GB User’s Manual
IBM Confidential
Ver 0.57, 24Mar95