Download 82C900 User`s Manual

82C900
Standalone TwinCAN Controller
Standalone TwinCAN Device
1.4.5
Interrupt Control
An interrupt request, generated by one of the 8 TwinCAN’s interrupt nodes, can be
indicated by output pins OUT0 and OUT1 or by the parallel I/O bus.
When bit field SELOUT0 (select output 0) in register GLOBCTR (global control) is set to
01B, output pin OUT0 is enabled to report an interrupt request. If control bit INTGR0
(interrupt group 0) is reset, only a request from interrupt node 0 is reported via output
OUT0. If INTGR0 is set to 1, all interrupt requests generated by interrupt node 0, 2, 4
and 6 are indicated via OUT0 and the external software has to identify the interrupt
request source by analyzing the interrupt control register INTCTR and the interrupt
pending registers AIR/BIR of the TwinCAN module. Depending on control bit INTGR1,
output pin OUT1 reports only an interrupt request generated by interrupt node 1 or
indicates all interrupt requests from interrupt node 1, 3, 5 and 7.
When the SSC is used as communication channel, the 8 pins of the parallel I/O bus can
be configured by bit fields IOM0..IOM7 in register IOMODE0/2 to report the interrupt
requests generated by the 8 interrupt nodes. This report source operates parallel to the
interrupt request indication via pins OUT0 or OUT1.
Register INTCTR indicates via flag INTi (i=0-7), which interrupt node has been activated.
An interrupt request flag INTi can be cleared by setting the corresponding INTRi bit in
register INTCTR to 1. Bit INTRi is automatically reset by hardware after bit INTi has been
cleared. Interrupt requests are generated at the interrupt output lines even if the
corresponding INTi flag is still set and has not been reset by software before (INTi only
for indication purpose).
The interrupt pulse driven by the selected interrupt output pin will have a length of 5
oscillator periods (TCAN).
User’s Manual
1-16
V1.0D2, 2000-12