Download SYS68K/CPU-60 Technical Reference Manual
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Hardware VMEbus Interface 3.15 VMEbus Interface The following sections describe the VMEbus interface in detail. This section gives a short overview of the VMEbus interface features. ANSI/VITA compliance The SYS68K/CPU-60 provides a complete VMEbus interface compliant with ANSI/VITA 1-1994. Supported transfers The VMEbus interface supports 8, 16, and 32 bit, as well as unaligned data transfers. The extended, standard, and short I/O address modifier codes are implemented to interface the SYS68K/CPU-60 to all existing VMEbus products. RMW cycles Read-modify-write cycles on the VMEbus (RMW cycles) are also supported. The address strobe signal is held low during RMW cycles while the data strobe signals are driven low twice, once for the read cycle and once for the write cycle, and high between both of them. Interrupt handler The complete VMEbus interrupt management is done by the FGA-002 enabling the use of a high-end multiprocessor environment board with distributed interrupt handling. The FGA-002 acts as D08(O) interrupt handler in compliance with the VMEbus specification. 16-bit interrupt vectors are not supported. All 7 VMEbus interrupt request (IRQ) signals are connected to the interrupt handling logic on the FGA-002. • All 7 VMEbus IRQ signals can be separately enabled or disabled. • Every VMEbus interrupt request level can be mapped to cause an interrupt to the processor on a different level. For example, a VMEbus interrupt request on level 2 (IRQ2*) can be mapped to cause an interrupt request to the 68060 CPU on level 5. Slot-1 A single-level bus arbiter together with several release functions is implemented with all slot-1 system controller functions (see section 3.17 “VMEbus Slot-1” on page 86): • SYSRESET* driver and receiver, • SYSCLK driver, • and IACK daisy-chain driver (see below). IACK Daisy Chain Driver In accordance with the VMEbus specification the CPU board includes an IACK daisy-chain driver. If the CPU board is plugged in slot 1 and configured accordingly by SW6-1 and SW6-2, the board acts as IACK daisychain driver. Plugged in any other slot the board closes the IACKINIACKOUT path. SYS68K/CPU-60 Page 75