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to display them for the VGA. This means that wider data buses will take up more FPGA register space
than smaller buses and more logic resources will be required to manipulate them. Since the Cyclone II
is not a large FPGA, a smaller bus width would be preferable. With these considerations in mind,
several ICs were examined, and an 8 bit, single sided ADC and an equivalent DAC were selected.
The other significant hardware trade off was how to structure the analog signal paths. Adding
amplification stages can add flexibility to a design, but also increases the complexity and the number of
points of failure in this untested design. A direct connection avoids these pitfalls, but offers no way to
manipulate the signals in analog space. Filtering was not considered, as digital filters can be
implemented in the FPGA. The solution chosen was to provide both a direct path and an amplified
path for each converter. The user can select between them by switching a set of jumpers. This
approach combines the benefits of analog manipulation with a backup direct path at little extra design
time cost.
The main software design decision was where to put the stored values for display on the FPGA.
The Cyclone II FPGA has both internal registers and RAM units as well as a large external RAM.
Typical VGA applications use the external ram to store a screen's worth of information, as there is not
enough internal memory for a 640x480, 8-bit deep matrix. In this case, however, only one 640-element
line of 8-bit values was needed. The stored values correspond not to pixel intensity, but to the
magnitude of the voltage at each screen column and which row pixel should be lit. Other on screen
elements, such as time and voltage divisions, can be procedurally generated rather than stored. This
permits the use of a large array register or of internal memory to store the signal data. Initial tests
indicated that the large register constructs were expensive in terms of logic, but allowed fast parallel
manipulation and simple programming. Memory, on the other hand, was placed in reserved space on
the chip and was easy to synthesize, but could only be read or written once per cycle. Both techniques
were eventually used in the final design. A register array was created to read in the ADC values and
allow them to be shuffled all at once while the input waited to be triggered. A memory array was
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